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/openbmc/linux/arch/mips/mm/
H A DMakefile62cedc4f Tue Jan 31 11:18:45 CST 2012 Florian Fainelli <florian@openwrt.org> MIPS: introduce CPU_R4K_CACHE_TLB

R4K-style CPUs having common code to support their caches and tlb have this
boolean defined by default. Allows us to remove some lines in
arch/mips/mm/Makefile.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/3328/
Signed-off-by: John Crispin <blogic@openwrt.org>
62cedc4f Tue Jan 31 11:18:45 CST 2012 Florian Fainelli <florian@openwrt.org> MIPS: introduce CPU_R4K_CACHE_TLB

R4K-style CPUs having common code to support their caches and tlb have this
boolean defined by default. Allows us to remove some lines in
arch/mips/mm/Makefile.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/3328/
Signed-off-by: John Crispin <blogic@openwrt.org>
/openbmc/linux/arch/mips/
H A DKconfig62cedc4f Tue Jan 31 11:18:45 CST 2012 Florian Fainelli <florian@openwrt.org> MIPS: introduce CPU_R4K_CACHE_TLB

R4K-style CPUs having common code to support their caches and tlb have this
boolean defined by default. Allows us to remove some lines in
arch/mips/mm/Makefile.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/3328/
Signed-off-by: John Crispin <blogic@openwrt.org>
62cedc4f Tue Jan 31 11:18:45 CST 2012 Florian Fainelli <florian@openwrt.org> MIPS: introduce CPU_R4K_CACHE_TLB

R4K-style CPUs having common code to support their caches and tlb have this
boolean defined by default. Allows us to remove some lines in
arch/mips/mm/Makefile.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/3328/
Signed-off-by: John Crispin <blogic@openwrt.org>