Searched hist:"616 bc1dea1ac8909dfcd6d32802df6fe50eddde8" (Results 1 – 4 of 4) sorted by relevance
| /openbmc/linux/drivers/clk/starfive/ |
| H A D | clk-starfive-jh7110-pll.c | 616bc1dea1ac8909dfcd6d32802df6fe50eddde8 Sun Jul 16 21:30:37 CDT 2023 Xingyu Wu <xingyu.wu@starfivetech.com> clk: starfive: Add StarFive JH7110 PLL clock driver
Add driver for the StarFive JH7110 PLL clock controller
and they work by reading and setting syscon registers.
Co-developed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| H A D | Makefile | 616bc1dea1ac8909dfcd6d32802df6fe50eddde8 Sun Jul 16 21:30:37 CDT 2023 Xingyu Wu <xingyu.wu@starfivetech.com> clk: starfive: Add StarFive JH7110 PLL clock driver
Add driver for the StarFive JH7110 PLL clock controller
and they work by reading and setting syscon registers.
Co-developed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| H A D | Kconfig | 616bc1dea1ac8909dfcd6d32802df6fe50eddde8 Sun Jul 16 21:30:37 CDT 2023 Xingyu Wu <xingyu.wu@starfivetech.com> clk: starfive: Add StarFive JH7110 PLL clock driver
Add driver for the StarFive JH7110 PLL clock controller
and they work by reading and setting syscon registers.
Co-developed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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| /openbmc/linux/ |
| H A D | MAINTAINERS | 616bc1dea1ac8909dfcd6d32802df6fe50eddde8 Sun Jul 16 21:30:37 CDT 2023 Xingyu Wu <xingyu.wu@starfivetech.com> clk: starfive: Add StarFive JH7110 PLL clock driver
Add driver for the StarFive JH7110 PLL clock controller
and they work by reading and setting syscon registers.
Co-developed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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