Searched hist:"5686 b06c" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/arch/arm64/include/asm/ |
| H A D | spinlock.h | 5686b06c Wed Oct 09 09:54:27 CDT 2013 Will Deacon <will.deacon@arm.com> arm64: lockref: add support for lockless lockrefs using cmpxchg
Our spinlocks are only 32-bit (2x16-bit tickets) and our cmpxchg can
deal with 8-bytes (as one would hope!).
This patch wires up the cmpxchg-based lockless lockref implementation
for arm64.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
5686b06c Wed Oct 09 09:54:27 CDT 2013 Will Deacon <will.deacon@arm.com> arm64: lockref: add support for lockless lockrefs using cmpxchg
Our spinlocks are only 32-bit (2x16-bit tickets) and our cmpxchg can
deal with 8-bytes (as one would hope!).
This patch wires up the cmpxchg-based lockless lockref implementation
for arm64.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
|
| /openbmc/linux/arch/arm64/ |
| H A D | Kconfig | 5686b06c Wed Oct 09 09:54:27 CDT 2013 Will Deacon <will.deacon@arm.com> arm64: lockref: add support for lockless lockrefs using cmpxchg
Our spinlocks are only 32-bit (2x16-bit tickets) and our cmpxchg can
deal with 8-bytes (as one would hope!).
This patch wires up the cmpxchg-based lockless lockref implementation
for arm64.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
|