Searched hist:"4 ca06607" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/u-boot/board/freescale/mpc8572ds/ |
| H A D | ddr.c | 4ca06607 Fri Oct 03 11:37:41 CDT 2008 Haiying Wang <Haiying.Wang@freescale.com> Add ddr interleaving suppport for MPC8572DS board
* Add board specific parameter table to choose correct cpo, clk_adjust,
write_data_delay, 2T based on board ddr frequency and n_ranks.
* Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#.
* Set memory controller interleaving mode to bank interleaving, and disable
bank(chip select) interleaving mode by default, because the default on-board
DDR DIMMs are 2x512MB single-rank.
* Change CONFIG_ICS307_REFCLK_HZ from 33333333 to 33333000.
Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
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| /openbmc/u-boot/include/configs/ |
| H A D | MPC8572DS.h | 4ca06607 Fri Oct 03 11:37:41 CDT 2008 Haiying Wang <Haiying.Wang@freescale.com> Add ddr interleaving suppport for MPC8572DS board
* Add board specific parameter table to choose correct cpo, clk_adjust,
write_data_delay, 2T based on board ddr frequency and n_ranks.
* Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#.
* Set memory controller interleaving mode to bank interleaving, and disable
bank(chip select) interleaving mode by default, because the default on-board
DDR DIMMs are 2x512MB single-rank.
* Change CONFIG_ICS307_REFCLK_HZ from 33333333 to 33333000.
Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
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