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H A D | gdbstub.c | 4a909912 Wed Mar 27 21:23:12 CDT 2024 Jason Chien <jason.chien@sifive.com> target/riscv: Relax vector register check in RISCV gdbstub
In current implementation, the gdbstub allows reading vector registers only if V extension is supported. However, all vector extensions and vector crypto extensions have the vector registers and they all depend on Zve32x. The gdbstub should check for Zve32x instead.
Signed-off-by: Jason Chien <jason.chien@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Max Chou <max.chou@sifive.com> Message-ID: <20240328022343.6871-4-jason.chien@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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