Searched hist:"4 a3dcd35" (Results 1 – 1 of 1) sorted by relevance
| /openbmc/linux/arch/arm/mach-pxa/ |
| H A D | irq.c | 4a3dcd35 Wed Jun 06 00:45:18 CDT 2007 Eric Miao <eric.y.miao@gmail.com> [ARM] 4438/1: PXA: remove #ifdef .. #endif from pxa_gpio_demux_handler()
1. use GPIO_IRQ_mask[] to select those bits of interest, actually
only those "unmasked" GPIO IRQs with their corresponding bits
in GPIO_IRQ_mask[] set to "1" should be checked
2. remove #ifdef PXA_LAST_GPIO > 96 .. #endif, GPIO_IRQ_mask[]
is used to mask out the irrelevant bits, so that even though
the GEDR3 on PXA25x is reserved, it will be masked, and the
following code will never run. Another point is that GPIO85-
GPIO95 bits within GEDR2 will also be masked out on PXA25x
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
4a3dcd35 Wed Jun 06 00:45:18 CDT 2007 Eric Miao <eric.y.miao@gmail.com> [ARM] 4438/1: PXA: remove #ifdef .. #endif from pxa_gpio_demux_handler()
1. use GPIO_IRQ_mask[] to select those bits of interest, actually
only those "unmasked" GPIO IRQs with their corresponding bits
in GPIO_IRQ_mask[] set to "1" should be checked
2. remove #ifdef PXA_LAST_GPIO > 96 .. #endif, GPIO_IRQ_mask[]
is used to mask out the irrelevant bits, so that even though
the GEDR3 on PXA25x is reserved, it will be masked, and the
following code will never run. Another point is that GPIO85-
GPIO95 bits within GEDR2 will also be masked out on PXA25x
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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