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| /openbmc/linux/drivers/clk/samsung/ |
| H A D | clk-exynos5420.c | 45f10dab Fri Oct 25 04:34:35 CDT 2019 Marek Szyprowski <m.szyprowski@samsung.com> clk: samsung: exynos5420: Add SET_RATE_PARENT flag to clocks on G3D path
Add CLK_SET_RATE_PARENT flag to all clocks on the path from VPLL to G3D,
so the G3D MALI driver can simply adjust the rate of its clock by doing
a single clk_set_rate() call, without the need to know the whole clock
topology in Exynos542x SoCs.
Suggested-by: Marian Mihailescu <mihailescu2m@gmail.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
45f10dab Fri Oct 25 04:34:35 CDT 2019 Marek Szyprowski <m.szyprowski@samsung.com> clk: samsung: exynos5420: Add SET_RATE_PARENT flag to clocks on G3D path
Add CLK_SET_RATE_PARENT flag to all clocks on the path from VPLL to G3D,
so the G3D MALI driver can simply adjust the rate of its clock by doing
a single clk_set_rate() call, without the need to know the whole clock
topology in Exynos542x SoCs.
Suggested-by: Marian Mihailescu <mihailescu2m@gmail.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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