Searched hist:"45 e077d7" (Results 1 – 2 of 2) sorted by relevance
/openbmc/qemu/accel/tcg/ |
H A D | meson.build | 45e077d7 Thu Oct 15 09:32:15 CDT 2020 Claudio Fontana <cfontana@suse.de> accel/tcg: split CpusAccel into three TCG variants split up the CpusAccel tcg_cpus into three TCG variants: tcg_cpus_rr (single threaded, round robin cpus) tcg_cpus_icount (same as rr, but with instruction counting enabled) tcg_cpus_mttcg (multi-threaded cpus) Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201015143217.29337-2-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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H A D | tcg-all.c | 45e077d7 Thu Oct 15 09:32:15 CDT 2020 Claudio Fontana <cfontana@suse.de> accel/tcg: split CpusAccel into three TCG variants split up the CpusAccel tcg_cpus into three TCG variants: tcg_cpus_rr (single threaded, round robin cpus) tcg_cpus_icount (same as rr, but with instruction counting enabled) tcg_cpus_mttcg (multi-threaded cpus) Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201015143217.29337-2-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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