Searched hist:"40 b27176" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/drivers/gpu/drm/i915/gvt/ |
| H A D | gtt.h | 40b27176 Mon May 14 21:35:36 CDT 2018 Changbin Du <changbin.du@intel.com> drm/i915/gvt: Detect 64K gtt entry by IPS bit of PDE
This change help us detect the real entry type per PSE and IPS setting.
For 64K entry, we also need to check reg GEN8_GAMW_ECO_DEV_RW_IA.
v2: Extend IPS mmio control to Gen10. (Matthew Auld)
Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
40b27176 Mon May 14 21:35:36 CDT 2018 Changbin Du <changbin.du@intel.com> drm/i915/gvt: Detect 64K gtt entry by IPS bit of PDE
This change help us detect the real entry type per PSE and IPS setting.
For 64K entry, we also need to check reg GEN8_GAMW_ECO_DEV_RW_IA.
v2: Extend IPS mmio control to Gen10. (Matthew Auld)
Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
|
| H A D | gtt.c | 40b27176 Mon May 14 21:35:36 CDT 2018 Changbin Du <changbin.du@intel.com> drm/i915/gvt: Detect 64K gtt entry by IPS bit of PDE
This change help us detect the real entry type per PSE and IPS setting.
For 64K entry, we also need to check reg GEN8_GAMW_ECO_DEV_RW_IA.
v2: Extend IPS mmio control to Gen10. (Matthew Auld)
Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
40b27176 Mon May 14 21:35:36 CDT 2018 Changbin Du <changbin.du@intel.com> drm/i915/gvt: Detect 64K gtt entry by IPS bit of PDE
This change help us detect the real entry type per PSE and IPS setting.
For 64K entry, we also need to check reg GEN8_GAMW_ECO_DEV_RW_IA.
v2: Extend IPS mmio control to Gen10. (Matthew Auld)
Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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