Searched hist:"4021 b438" (Results 1 – 3 of 3) sorted by relevance
| /openbmc/u-boot/arch/arm/mach-uniphier/dram/ |
| H A D | ddrphy-regs.h | 4021b438 Thu Feb 25 23:21:40 CST 2016 Masahiro Yamada <yamada.masahiro@socionext.com> ARM: uniphier: add a field to specify DDR3+
Add a field to distinguish DDR3+ from (standard) DDR3. It also
allows to delete CONFIG_DDR_STANDARD (this is not a software
configuration, but a board attribute).
Default DDR3 spec for each SoC:
PH1-LD4, PH1-sLD8: DDR3+
Others: DDR3
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| /openbmc/u-boot/arch/arm/mach-uniphier/ |
| H A D | boards.c | 4021b438 Thu Feb 25 23:21:40 CST 2016 Masahiro Yamada <yamada.masahiro@socionext.com> ARM: uniphier: add a field to specify DDR3+
Add a field to distinguish DDR3+ from (standard) DDR3. It also
allows to delete CONFIG_DDR_STANDARD (this is not a software
configuration, but a board attribute).
Default DDR3 spec for each SoC:
PH1-LD4, PH1-sLD8: DDR3+
Others: DDR3
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| H A D | init.h | 4021b438 Thu Feb 25 23:21:40 CST 2016 Masahiro Yamada <yamada.masahiro@socionext.com> ARM: uniphier: add a field to specify DDR3+
Add a field to distinguish DDR3+ from (standard) DDR3. It also
allows to delete CONFIG_DDR_STANDARD (this is not a software
configuration, but a board attribute).
Default DDR3 spec for each SoC:
PH1-LD4, PH1-sLD8: DDR3+
Others: DDR3
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|