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H A D | ccu-sun50i-h6.c | 4014e916 Wed Sep 28 15:01:22 CDT 2022 Jernej Skrabec <jernej.skrabec@gmail.com> clk: sunxi-ng: h6: Fix default PLL GPU rate
In commit 4167ac8a657e ("clk: sunxi-ng: sun50i: h6: Modify GPU clock configuration to support DFS") divider M0 was forced to be 1 in order to support DFS. However, that left N as it is, at high value of 36. On boards without devfreq enabled (all of them in kernel 6.0), this effectively sets GPU frequency to 864 MHz. This is about 100 MHz above maximum supported frequency.
In order to fix this, let's set N to 18 (register value 17). That way default frequency of 432 MHz is preserved.
Fixes: 4167ac8a657e ("clk: sunxi-ng: sun50i: h6: Modify GPU clock configuration to support DFS") Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220928200122.3963509-1-jernej.skrabec@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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