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| H A D | irq-gic-v3-its.c | 3fca09b6 Mon Oct 30 03:32:56 CDT 2023 Fang Xiang <fangxiang3@xiaomi.com> irqchip/gic-v3-its: Flush ITS tables correctly in non-coherent GIC designs
[ Upstream commit d3badb15613c14dd35d3495b1dde5c90fcd616dd ]
In non-coherent GIC designs, the ITS tables must be flushed before writing
to the GITS_BASER<n> registers, otherwise the ITS could read dirty tables,
which results in unpredictable behavior.
Flush the tables right at the begin of its_setup_baser() to prevent that.
[ tglx: Massage changelog ]
Fixes: a8707f553884 ("irqchip/gic-v3: Add Rockchip 3588001 erratum workaround")
Suggested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Fang Xiang <fangxiang3@xiaomi.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20231030083256.4345-1-fangxiang3@xiaomi.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
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