Searched hist:"337 fcdc0" (Results 1 – 3 of 3) sorted by relevance
| /openbmc/u-boot/drivers/clk/sunxi/ |
| H A D | clk_h6.c | 337fcdc0 Mon Dec 31 04:05:01 CST 2018 Jagan Teki <jagan@amarulasolutions.com> clk: sunxi: Add Allwinner H6 CLK driver
Add initial clock driver for Allwinner H6.
- Implement UART bus clocks via ccu_clk_gate table for
H6, so it can accessed in common clk enable and disable
functions from clk_sunxi.c
- Implement UART bus resets via ccu_reset table for H6,
so it can accessed in common reset deassert and assert
functions from reset-sunxi.c
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
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| H A D | Kconfig | 337fcdc0 Mon Dec 31 04:05:01 CST 2018 Jagan Teki <jagan@amarulasolutions.com> clk: sunxi: Add Allwinner H6 CLK driver
Add initial clock driver for Allwinner H6.
- Implement UART bus clocks via ccu_clk_gate table for
H6, so it can accessed in common clk enable and disable
functions from clk_sunxi.c
- Implement UART bus resets via ccu_reset table for H6,
so it can accessed in common reset deassert and assert
functions from reset-sunxi.c
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
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| H A D | Makefile | 337fcdc0 Mon Dec 31 04:05:01 CST 2018 Jagan Teki <jagan@amarulasolutions.com> clk: sunxi: Add Allwinner H6 CLK driver
Add initial clock driver for Allwinner H6.
- Implement UART bus clocks via ccu_clk_gate table for
H6, so it can accessed in common clk enable and disable
functions from clk_sunxi.c
- Implement UART bus resets via ccu_reset table for H6,
so it can accessed in common reset deassert and assert
functions from reset-sunxi.c
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
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