Searched hist:"32 af01f8" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/qemu/hw/intc/ |
| H A D | pnv_xive2_regs.h | 32af01f8 Thu Jun 01 07:13:28 CDT 2023 Frederic Barrat <fbarrat@linux.ibm.com> pnv/xive2: Add definition for the ESB cache configuration register
Add basic read/write support for the ESB cache configuration register
on P10. We don't model the ESB cache in qemu so reading/writing the
register won't do anything, but it avoids logging a guest error when
skiboot configures it:
qemu-system-ppc64 -machine powernv10 ... -d guest_errors
...
XIVE[0] - VC: invalid read @240
XIVE[0] - VC: invalid write @240
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20230601121331.487207-3-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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| H A D | pnv_xive2.c | 32af01f8 Thu Jun 01 07:13:28 CDT 2023 Frederic Barrat <fbarrat@linux.ibm.com> pnv/xive2: Add definition for the ESB cache configuration register
Add basic read/write support for the ESB cache configuration register
on P10. We don't model the ESB cache in qemu so reading/writing the
register won't do anything, but it avoids logging a guest error when
skiboot configures it:
qemu-system-ppc64 -machine powernv10 ... -d guest_errors
...
XIVE[0] - VC: invalid read @240
XIVE[0] - VC: invalid write @240
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20230601121331.487207-3-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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