Searched hist:"306 e5e50" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/arch/openrisc/configs/ |
| H A D | simple_smp_defconfig | 306e5e50 Sun May 18 02:54:47 CDT 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> openrisc: add simple_smp dts and defconfig for simulators
Simple enough to be compatible with simulation environments,
such as verilated systems, QEMU and other targets supporting OpenRISC
SMP. This also supports our base FPGA SoC's if the cpu frequency is
upped to 50Mhz.
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
[shorne@gmail.com: Added defconfig]
Signed-off-by: Stafford Horne <shorne@gmail.com>
306e5e50 Sun May 18 02:54:47 CDT 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> openrisc: add simple_smp dts and defconfig for simulators
Simple enough to be compatible with simulation environments,
such as verilated systems, QEMU and other targets supporting OpenRISC
SMP. This also supports our base FPGA SoC's if the cpu frequency is
upped to 50Mhz.
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
[shorne@gmail.com: Added defconfig]
Signed-off-by: Stafford Horne <shorne@gmail.com>
|
| /openbmc/linux/arch/openrisc/boot/dts/ |
| H A D | simple_smp.dts | 306e5e50 Sun May 18 02:54:47 CDT 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> openrisc: add simple_smp dts and defconfig for simulators
Simple enough to be compatible with simulation environments,
such as verilated systems, QEMU and other targets supporting OpenRISC
SMP. This also supports our base FPGA SoC's if the cpu frequency is
upped to 50Mhz.
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
[shorne@gmail.com: Added defconfig]
Signed-off-by: Stafford Horne <shorne@gmail.com>
306e5e50 Sun May 18 02:54:47 CDT 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> openrisc: add simple_smp dts and defconfig for simulators
Simple enough to be compatible with simulation environments,
such as verilated systems, QEMU and other targets supporting OpenRISC
SMP. This also supports our base FPGA SoC's if the cpu frequency is
upped to 50Mhz.
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
[shorne@gmail.com: Added defconfig]
Signed-off-by: Stafford Horne <shorne@gmail.com>
|