Searched hist:"3068 bec8" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/drivers/gpu/drm/i915/gt/ |
| H A D | intel_gt_mcr.h | 3068bec8 Fri Oct 14 18:02:32 CDT 2022 Matt Roper <matthew.d.roper@intel.com> drm/i915/gt: Add intel_gt_mcr_wait_for_reg_fw()
Xe_HP has some MCR registers that need to be polled for completion of
operations like TLB invalidation. Those registers are in the GAM range,
which rolls up the status from each unit into the 'primary' instance's
value. This makes it useful to have a dedicated 'wait for register'
function that handles this on MCR registers, similar to the
__intel_wait_for_register_fw() function we already have for regular
registers.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221014230239.1023689-8-matthew.d.roper@intel.com
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| H A D | intel_gt_mcr.c | 3068bec8 Fri Oct 14 18:02:32 CDT 2022 Matt Roper <matthew.d.roper@intel.com> drm/i915/gt: Add intel_gt_mcr_wait_for_reg_fw()
Xe_HP has some MCR registers that need to be polled for completion of
operations like TLB invalidation. Those registers are in the GAM range,
which rolls up the status from each unit into the 'primary' instance's
value. This makes it useful to have a dedicated 'wait for register'
function that handles this on MCR registers, similar to the
__intel_wait_for_register_fw() function we already have for regular
registers.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221014230239.1023689-8-matthew.d.roper@intel.com
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