Searched hist:"2 e4ce50d" (Results 1 – 3 of 3) sorted by relevance
| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | rv1108-cru.h | 2e4ce50d Wed Sep 20 01:28:18 CDT 2017 David Wu <david.wu@rock-chips.com> rockchip: clk: Add rv1108 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | cru_rv1108.h | 2e4ce50d Wed Sep 20 01:28:18 CDT 2017 David Wu <david.wu@rock-chips.com> rockchip: clk: Add rv1108 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
|
| /openbmc/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rv1108.c | 2e4ce50d Wed Sep 20 01:28:18 CDT 2017 David Wu <david.wu@rock-chips.com> rockchip: clk: Add rv1108 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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