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/openbmc/u-boot/doc/device-tree-bindings/misc/
H A Dintel-lpc.txt2b605154 Wed Nov 12 23:42:15 CST 2014 Simon Glass <sjg@chromium.org> x86: ivybridge: Add early LPC init so that serial works

The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device
which provides a serial port. This is accessible on Chromebooks, so enable
it early in the boot process.

Signed-off-by: Simon Glass <sjg@chromium.org>
/openbmc/u-boot/arch/x86/include/asm/arch-ivybridge/
H A Dpch.h2b605154 Wed Nov 12 23:42:15 CST 2014 Simon Glass <sjg@chromium.org> x86: ivybridge: Add early LPC init so that serial works

The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device
which provides a serial port. This is accessible on Chromebooks, so enable
it early in the boot process.

Signed-off-by: Simon Glass <sjg@chromium.org>
/openbmc/u-boot/arch/x86/cpu/ivybridge/
H A Dlpc.c2b605154 Wed Nov 12 23:42:15 CST 2014 Simon Glass <sjg@chromium.org> x86: ivybridge: Add early LPC init so that serial works

The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device
which provides a serial port. This is accessible on Chromebooks, so enable
it early in the boot process.

Signed-off-by: Simon Glass <sjg@chromium.org>
H A DMakefile2b605154 Wed Nov 12 23:42:15 CST 2014 Simon Glass <sjg@chromium.org> x86: ivybridge: Add early LPC init so that serial works

The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device
which provides a serial port. This is accessible on Chromebooks, so enable
it early in the boot process.

Signed-off-by: Simon Glass <sjg@chromium.org>
H A Dcpu.c2b605154 Wed Nov 12 23:42:15 CST 2014 Simon Glass <sjg@chromium.org> x86: ivybridge: Add early LPC init so that serial works

The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device
which provides a serial port. This is accessible on Chromebooks, so enable
it early in the boot process.

Signed-off-by: Simon Glass <sjg@chromium.org>