Searched hist:"2 b3f7864" (Results 1 – 1 of 1) sorted by relevance
| /openbmc/linux/arch/riscv/configs/ |
| H A D | defconfig | 2b3f7864 Tue Dec 04 07:55:06 CST 2018 Anup Patel <anup@brainfault.org> RISC-V: defconfig: Enable RISC-V SBI earlycon support
This patch enables RISC-V SBI earlycon support in default defconfig
so that we can use "earlycon=sbi" in kernel parameters for early
debug prints.
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2b3f7864 Tue Dec 04 07:55:06 CST 2018 Anup Patel <anup@brainfault.org> RISC-V: defconfig: Enable RISC-V SBI earlycon support
This patch enables RISC-V SBI earlycon support in default defconfig
so that we can use "earlycon=sbi" in kernel parameters for early
debug prints.
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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