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/openbmc/linux/drivers/net/ethernet/mellanox/mlx5/core/steering/ |
H A D | dr_icm_pool.c | 29cf8feb Mon Aug 19 05:46:40 CDT 2019 Alex Vesker <valex@mellanox.com> net/mlx5: DR, ICM pool memory allocator
ICM device memory is used for writing steering rules (STEs) to the NIC. An ICM memory pool allocator was implemented to manage the required memory. The pool consists of buckets, a bucket per chunk size. Once a bucket is empty we will cut a row of memory from the latest allocated MR, if the MR size is not sufficient we will allocate a new MR. HW design requires that chunks memory address should be aligned to the chunk size, this is the reason for managing the MR with row size that insures memory alignment. Current design is greedy in memory but provides quick allocation times in steady state.
Signed-off-by: Alex Vesker <valex@mellanox.com> Reviewed-by: Erez Shitrit <erezsh@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> 29cf8feb Mon Aug 19 05:46:40 CDT 2019 Alex Vesker <valex@mellanox.com> net/mlx5: DR, ICM pool memory allocator ICM device memory is used for writing steering rules (STEs) to the NIC. An ICM memory pool allocator was implemented to manage the required memory. The pool consists of buckets, a bucket per chunk size. Once a bucket is empty we will cut a row of memory from the latest allocated MR, if the MR size is not sufficient we will allocate a new MR. HW design requires that chunks memory address should be aligned to the chunk size, this is the reason for managing the MR with row size that insures memory alignment. Current design is greedy in memory but provides quick allocation times in steady state. Signed-off-by: Alex Vesker <valex@mellanox.com> Reviewed-by: Erez Shitrit <erezsh@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
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