Searched hist:"27 c22b2d" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/qemu/include/hw/riscv/ |
| H A D | microchip_pfsoc.h | 27c22b2d Wed Oct 28 00:30:08 CDT 2020 Bin Meng <bin.meng@windriver.com> hw/riscv: microchip_pfsoc: Map the reserved memory at address 0
Somehow HSS needs to access address 0 [1] for the DDR calibration data
which is in the chipset's reserved memory. Let's map it.
[1] See the config_copy() calls in various places in ddr_setup() in
the HSS source codes.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-9-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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| /openbmc/qemu/hw/riscv/ |
| H A D | microchip_pfsoc.c | 27c22b2d Wed Oct 28 00:30:08 CDT 2020 Bin Meng <bin.meng@windriver.com> hw/riscv: microchip_pfsoc: Map the reserved memory at address 0
Somehow HSS needs to access address 0 [1] for the DDR calibration data
which is in the chipset's reserved memory. Let's map it.
[1] See the config_copy() calls in various places in ddr_setup() in
the HSS source codes.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-9-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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