Searched hist:"20 a58ac0" (Results 1 – 3 of 3) sorted by relevance
| /openbmc/u-boot/arch/arc/include/asm/ |
| H A D | sections.h | 20a58ac0 Wed Dec 24 08:17:11 CST 2014 Igor Guryanov <guryanov@synopsys.com> arc: introduce separate section for interrupt vector table
Even though existing implementation works fine in preparation to
submission of ARCv2 architecture we need this change.
In case of ARCv2 interrupt vector table consists of just addresses
of corresponding handlers. And if those addresses will be in .text
section then assembler will encode them as everything in .text section
as middle-endian and then on real execution CPU will read swapped
addresses and will jump into the wild.
Once introduced new section is situated so .text section remains the
first which allows us to use common linker option for linking everything
to a specified CONFIG_SYS_TEXT_BASE.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
|
| /openbmc/u-boot/arch/arc/ |
| H A D | Makefile | 20a58ac0 Wed Dec 24 08:17:11 CST 2014 Igor Guryanov <guryanov@synopsys.com> arc: introduce separate section for interrupt vector table
Even though existing implementation works fine in preparation to
submission of ARCv2 architecture we need this change.
In case of ARCv2 interrupt vector table consists of just addresses
of corresponding handlers. And if those addresses will be in .text
section then assembler will encode them as everything in .text section
as middle-endian and then on real execution CPU will read swapped
addresses and will jump into the wild.
Once introduced new section is situated so .text section remains the
first which allows us to use common linker option for linking everything
to a specified CONFIG_SYS_TEXT_BASE.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
|
| /openbmc/u-boot/arch/arc/lib/ |
| H A D | relocate.c | 20a58ac0 Wed Dec 24 08:17:11 CST 2014 Igor Guryanov <guryanov@synopsys.com> arc: introduce separate section for interrupt vector table
Even though existing implementation works fine in preparation to
submission of ARCv2 architecture we need this change.
In case of ARCv2 interrupt vector table consists of just addresses
of corresponding handlers. And if those addresses will be in .text
section then assembler will encode them as everything in .text section
as middle-endian and then on real execution CPU will read swapped
addresses and will jump into the wild.
Once introduced new section is situated so .text section remains the
first which allows us to use common linker option for linking everything
to a specified CONFIG_SYS_TEXT_BASE.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
|