Searched hist:"1 fb344a3" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/sound/soc/intel/skylake/ |
| H A D | skl-sst-dsp.c | 1fb344a3 Mon Mar 13 11:41:26 CDT 2017 Jeeja KP <jeeja.kp@intel.com> ASoC: Intel: bxtn: Update DSP core state in D0
In system suspend, firmware needs to be re-downloaded as IMR is cleared.
When firmware is downloaded in D0, core state is not set to running
state causing instability with subsequent D0-D3 cycles.
So set the core state correctly during D0 and check the DSP core state
if not in reset to set the DSP to D3.
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Acked-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
1fb344a3 Mon Mar 13 11:41:26 CDT 2017 Jeeja KP <jeeja.kp@intel.com> ASoC: Intel: bxtn: Update DSP core state in D0
In system suspend, firmware needs to be re-downloaded as IMR is cleared.
When firmware is downloaded in D0, core state is not set to running
state causing instability with subsequent D0-D3 cycles.
So set the core state correctly during D0 and check the DSP core state
if not in reset to set the DSP to D3.
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Acked-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
|
| H A D | bxt-sst.c | 1fb344a3 Mon Mar 13 11:41:26 CDT 2017 Jeeja KP <jeeja.kp@intel.com> ASoC: Intel: bxtn: Update DSP core state in D0
In system suspend, firmware needs to be re-downloaded as IMR is cleared.
When firmware is downloaded in D0, core state is not set to running
state causing instability with subsequent D0-D3 cycles.
So set the core state correctly during D0 and check the DSP core state
if not in reset to set the DSP to D3.
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Acked-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
1fb344a3 Mon Mar 13 11:41:26 CDT 2017 Jeeja KP <jeeja.kp@intel.com> ASoC: Intel: bxtn: Update DSP core state in D0
In system suspend, firmware needs to be re-downloaded as IMR is cleared.
When firmware is downloaded in D0, core state is not set to running
state causing instability with subsequent D0-D3 cycles.
So set the core state correctly during D0 and check the DSP core state
if not in reset to set the DSP to D3.
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Acked-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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