Searched hist:"1 f93a6e4" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/qemu/include/hw/misc/ |
| H A D | mips_cpc.h | 1f93a6e4 Tue Mar 15 04:59:30 CDT 2016 Leon Alrae <leon.alrae@imgtec.com> hw/mips: add initial Cluster Power Controller support
Cluster Power Controller (CPC) is responsible for power management in
multiprocessing system. It provides registers to control the power and the
clock frequency of the individual elements in the system.
This patch implements only three registers that are used to control the
power state of each VP on a single core:
* VP Run is a write-only register used to set each VP to the run state
* VP Stop is a write-only register used to set each VP to the suspend state
* VP Running is a read-only register indicating the run state of each VP
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
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| /openbmc/qemu/hw/misc/ |
| H A D | mips_cpc.c | 1f93a6e4 Tue Mar 15 04:59:30 CDT 2016 Leon Alrae <leon.alrae@imgtec.com> hw/mips: add initial Cluster Power Controller support
Cluster Power Controller (CPC) is responsible for power management in
multiprocessing system. It provides registers to control the power and the
clock frequency of the individual elements in the system.
This patch implements only three registers that are used to control the
power state of each VP on a single core:
* VP Run is a write-only register used to set each VP to the run state
* VP Stop is a write-only register used to set each VP to the suspend state
* VP Running is a read-only register indicating the run state of each VP
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
|