Searched hist:"1 ba62f10" (Results 1 – 4 of 4) sorted by relevance
| /openbmc/u-boot/board/freescale/p1010rdb/ |
| H A D | ddr.c | 1ba62f10 Wed Feb 29 06:36:51 CST 2012 York Sun <yorksun@freescale.com> powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards
P1010RDB and p1_pc_rdb_pc has incorrect configuration for
CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING.
Incorrect setting causes DDR failure in case of SPD absent.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| /openbmc/u-boot/board/freescale/p1_p2_rdb_pc/ |
| H A D | ddr.c | 1ba62f10 Wed Feb 29 06:36:51 CST 2012 York Sun <yorksun@freescale.com> powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards
P1010RDB and p1_pc_rdb_pc has incorrect configuration for
CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING.
Incorrect setting causes DDR failure in case of SPD absent.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| /openbmc/u-boot/include/configs/ |
| H A D | P1010RDB.h | 1ba62f10 Wed Feb 29 06:36:51 CST 2012 York Sun <yorksun@freescale.com> powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards
P1010RDB and p1_pc_rdb_pc has incorrect configuration for
CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING.
Incorrect setting causes DDR failure in case of SPD absent.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| H A D | p1_p2_rdb_pc.h | 1ba62f10 Wed Feb 29 06:36:51 CST 2012 York Sun <yorksun@freescale.com> powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards
P1010RDB and p1_pc_rdb_pc has incorrect configuration for
CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING.
Incorrect setting causes DDR failure in case of SPD absent.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|