Searched hist:"1 b8fc5a5" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/drivers/usb/chipidea/ |
| H A D | ci_hdrc_msm.c | 1b8fc5a5 Wed Dec 28 16:57:05 CST 2016 Stephen Boyd <stephen.boyd@linaro.org> usb: chipidea: msm: Add reset controller for PHY POR bit
The MSM chipidea wrapper has two bits that are used to reset the
first or second phy. Add support for these bits via the reset
controller framework, so that phy drivers can reset their
hardware at the right time during initialization.
Acked-by: Peter Chen <peter.chen@nxp.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
1b8fc5a5 Wed Dec 28 16:57:05 CST 2016 Stephen Boyd <stephen.boyd@linaro.org> usb: chipidea: msm: Add reset controller for PHY POR bit
The MSM chipidea wrapper has two bits that are used to reset the
first or second phy. Add support for these bits via the reset
controller framework, so that phy drivers can reset their
hardware at the right time during initialization.
Acked-by: Peter Chen <peter.chen@nxp.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
|
| H A D | Kconfig | 1b8fc5a5 Wed Dec 28 16:57:05 CST 2016 Stephen Boyd <stephen.boyd@linaro.org> usb: chipidea: msm: Add reset controller for PHY POR bit
The MSM chipidea wrapper has two bits that are used to reset the
first or second phy. Add support for these bits via the reset
controller framework, so that phy drivers can reset their
hardware at the right time during initialization.
Acked-by: Peter Chen <peter.chen@nxp.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
1b8fc5a5 Wed Dec 28 16:57:05 CST 2016 Stephen Boyd <stephen.boyd@linaro.org> usb: chipidea: msm: Add reset controller for PHY POR bit
The MSM chipidea wrapper has two bits that are used to reset the
first or second phy. Add support for these bits via the reset
controller framework, so that phy drivers can reset their
hardware at the right time during initialization.
Acked-by: Peter Chen <peter.chen@nxp.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
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