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H A D | tlv320aic32x4-clk.c | 11e756cc Sun Aug 13 07:55:20 CDT 2023 Guiting Shen <aarongt.shen@gmail.com> ASoC: tlv320aic32x4: Fix the divide by zero
The value of register(NDAC,MDAC,NADC,MADC,BCLKN) maybe zero lead to divide by zero in clk_aic32x4_div_recalc_rate().And the rate should be divide by 128 if the value was zero in this function according to the datasheet.
Add the macro AIC32X4_DIV_MAX to present the 128 and return 0 if failing to read the value of register.
Signed-off-by: Guiting Shen <aarongt.shen@gmail.com> Link: https://lore.kernel.org/r/20230813125520.11067-1-aarongt.shen@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
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H A D | tlv320aic32x4.h | 11e756cc Sun Aug 13 07:55:20 CDT 2023 Guiting Shen <aarongt.shen@gmail.com> ASoC: tlv320aic32x4: Fix the divide by zero
The value of register(NDAC,MDAC,NADC,MADC,BCLKN) maybe zero lead to divide by zero in clk_aic32x4_div_recalc_rate().And the rate should be divide by 128 if the value was zero in this function according to the datasheet.
Add the macro AIC32X4_DIV_MAX to present the 128 and return 0 if failing to read the value of register.
Signed-off-by: Guiting Shen <aarongt.shen@gmail.com> Link: https://lore.kernel.org/r/20230813125520.11067-1-aarongt.shen@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
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