Searched hist:"10 df8ff1" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/qemu/hw/xtensa/ |
| H A D | mx_pic.c | 10df8ff1 Sun Feb 17 06:38:58 CST 2013 Max Filippov <jcmvbkbc@gmail.com> target/xtensa: add MX interrupt controller
MX interrupt controller is a collection of the following devices
accessible through the external registers interface:
- interrupt distributor can route each external IRQ line to the
corresponding external IRQ pin of selected subset of connected xtensa
cores. It has per-CPU and per-IRQ enable signals and per-IRQ software
assert signals;
- IPI controller has 16 per-CPU IPI signals that may be routed to a
combination of 3 designated external IRQ pins of connected xtensa
cores;
- cache coherecy register controls core L1 cache participation in the
SMP cluster cache coherency protocol;
- runstall register lets BSP core stall and unstall AP cores.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
|
| /openbmc/qemu/include/hw/xtensa/ |
| H A D | mx_pic.h | 10df8ff1 Sun Feb 17 06:38:58 CST 2013 Max Filippov <jcmvbkbc@gmail.com> target/xtensa: add MX interrupt controller
MX interrupt controller is a collection of the following devices
accessible through the external registers interface:
- interrupt distributor can route each external IRQ line to the
corresponding external IRQ pin of selected subset of connected xtensa
cores. It has per-CPU and per-IRQ enable signals and per-IRQ software
assert signals;
- IPI controller has 16 per-CPU IPI signals that may be routed to a
combination of 3 designated external IRQ pins of connected xtensa
cores;
- cache coherecy register controls core L1 cache participation in the
SMP cluster cache coherency protocol;
- runstall register lets BSP core stall and unstall AP cores.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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