Searched hist:"10 ca61c6" (Results 1 – 4 of 4) sorted by relevance
| /openbmc/linux/arch/arm64/boot/dts/renesas/ |
| H A D | rzg2l-smarc-pinfunction.dtsi | 10ca61c6 Thu Jul 06 10:30:47 CDT 2023 Biju Das <biju.das.jz@bp.renesas.com> arm64: dts: renesas: rzg2l-smarc: Add support for enabling MTU3
Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/{G2,V2}L SMARC
EVK.
The MTU3a PWM pins are muxed with spi1 pins and counter external input
phase clock pins are muxed with scif2 pins. Disable these IPs when
PMOD_MTU3 macro is enabled.
Apart from this, the counter Z phase clock signal is muxed with the
SDHI1 cd signal. So disable SDHI1 IP, when the counter Z phase signal
is enabled.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230706153047.368993-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
| H A D | r9a07g044l2-smarc.dts | 10ca61c6 Thu Jul 06 10:30:47 CDT 2023 Biju Das <biju.das.jz@bp.renesas.com> arm64: dts: renesas: rzg2l-smarc: Add support for enabling MTU3
Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/{G2,V2}L SMARC
EVK.
The MTU3a PWM pins are muxed with spi1 pins and counter external input
phase clock pins are muxed with scif2 pins. Disable these IPs when
PMOD_MTU3 macro is enabled.
Apart from this, the counter Z phase clock signal is muxed with the
SDHI1 cd signal. So disable SDHI1 IP, when the counter Z phase signal
is enabled.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230706153047.368993-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
| H A D | r9a07g054l2-smarc.dts | 10ca61c6 Thu Jul 06 10:30:47 CDT 2023 Biju Das <biju.das.jz@bp.renesas.com> arm64: dts: renesas: rzg2l-smarc: Add support for enabling MTU3
Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/{G2,V2}L SMARC
EVK.
The MTU3a PWM pins are muxed with spi1 pins and counter external input
phase clock pins are muxed with scif2 pins. Disable these IPs when
PMOD_MTU3 macro is enabled.
Apart from this, the counter Z phase clock signal is muxed with the
SDHI1 cd signal. So disable SDHI1 IP, when the counter Z phase signal
is enabled.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230706153047.368993-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
| H A D | rzg2l-smarc.dtsi | 10ca61c6 Thu Jul 06 10:30:47 CDT 2023 Biju Das <biju.das.jz@bp.renesas.com> arm64: dts: renesas: rzg2l-smarc: Add support for enabling MTU3
Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/{G2,V2}L SMARC
EVK.
The MTU3a PWM pins are muxed with spi1 pins and counter external input
phase clock pins are muxed with scif2 pins. Disable these IPs when
PMOD_MTU3 macro is enabled.
Apart from this, the counter Z phase clock signal is muxed with the
SDHI1 cd signal. So disable SDHI1 IP, when the counter Z phase signal
is enabled.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230706153047.368993-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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