Searched hist:"0 d47bc70" (Results 1 – 7 of 7) sorted by relevance
| /openbmc/u-boot/arch/arm/include/asm/arch-sunxi/ |
| H A D | ccu.h | 0d47bc70 Sat Dec 22 10:02:49 CST 2018 Jagan Teki <jagan@amarulasolutions.com> clk: Add Allwinner A64 CLK driver
Add initial clock driver for Allwinner A64.
Implement USB clock enable and disable functions for
OHCI, EHCI, OTG and USBPHY gate and clock registers
via ccu clk gate table.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
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| /openbmc/u-boot/drivers/clk/sunxi/ |
| H A D | clk_sunxi.c | 0d47bc70 Sat Dec 22 10:02:49 CST 2018 Jagan Teki <jagan@amarulasolutions.com> clk: Add Allwinner A64 CLK driver
Add initial clock driver for Allwinner A64.
Implement USB clock enable and disable functions for
OHCI, EHCI, OTG and USBPHY gate and clock registers
via ccu clk gate table.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
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| H A D | clk_a64.c | 0d47bc70 Sat Dec 22 10:02:49 CST 2018 Jagan Teki <jagan@amarulasolutions.com> clk: Add Allwinner A64 CLK driver
Add initial clock driver for Allwinner A64.
Implement USB clock enable and disable functions for
OHCI, EHCI, OTG and USBPHY gate and clock registers
via ccu clk gate table.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
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| H A D | Kconfig | 0d47bc70 Sat Dec 22 10:02:49 CST 2018 Jagan Teki <jagan@amarulasolutions.com> clk: Add Allwinner A64 CLK driver
Add initial clock driver for Allwinner A64.
Implement USB clock enable and disable functions for
OHCI, EHCI, OTG and USBPHY gate and clock registers
via ccu clk gate table.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
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| H A D | Makefile | 0d47bc70 Sat Dec 22 10:02:49 CST 2018 Jagan Teki <jagan@amarulasolutions.com> clk: Add Allwinner A64 CLK driver
Add initial clock driver for Allwinner A64.
Implement USB clock enable and disable functions for
OHCI, EHCI, OTG and USBPHY gate and clock registers
via ccu clk gate table.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
|
| /openbmc/u-boot/drivers/clk/ |
| H A D | Kconfig | 0d47bc70 Sat Dec 22 10:02:49 CST 2018 Jagan Teki <jagan@amarulasolutions.com> clk: Add Allwinner A64 CLK driver
Add initial clock driver for Allwinner A64.
Implement USB clock enable and disable functions for
OHCI, EHCI, OTG and USBPHY gate and clock registers
via ccu clk gate table.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
|
| H A D | Makefile | 0d47bc70 Sat Dec 22 10:02:49 CST 2018 Jagan Teki <jagan@amarulasolutions.com> clk: Add Allwinner A64 CLK driver
Add initial clock driver for Allwinner A64.
Implement USB clock enable and disable functions for
OHCI, EHCI, OTG and USBPHY gate and clock registers
via ccu clk gate table.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
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