Searched hist:"0 bac5111" (Results 1 – 3 of 3) sorted by relevance
| /openbmc/linux/drivers/mtd/maps/ |
| H A D | intel_vr_nor.c | 0bac5111 Sun Sep 23 12:51:25 CDT 2007 David Woodhouse <dwmw2@infradead.org> [MTD] map driver for NOR flash on the Intel Vermilion Range chipset
The Vermilion Range Expansion Bus supports four chip selects, each of which
has 64MiB of address space. The 2nd BAR of the Expansion Bus PCI Device
is a 256MiB memory region containing the address spaces for all four of
the chip selects, with start addresses hardcoded on 64MiB boundaries.
This map driver only supports NOR flash on chip select 0. The buswidth
(either 8 bits or 16 bits) is determined by reading the Expansion Bus Timing
and Control Register for Chip Select 0 (EXP_TIMING_CS0).
Signed-off-by: Andy Lowe <alowe@mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
0bac5111 Sun Sep 23 12:51:25 CDT 2007 David Woodhouse <dwmw2@infradead.org> [MTD] map driver for NOR flash on the Intel Vermilion Range chipset
The Vermilion Range Expansion Bus supports four chip selects, each of which
has 64MiB of address space. The 2nd BAR of the Expansion Bus PCI Device
is a 256MiB memory region containing the address spaces for all four of
the chip selects, with start addresses hardcoded on 64MiB boundaries.
This map driver only supports NOR flash on chip select 0. The buswidth
(either 8 bits or 16 bits) is determined by reading the Expansion Bus Timing
and Control Register for Chip Select 0 (EXP_TIMING_CS0).
Signed-off-by: Andy Lowe <alowe@mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
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| H A D | Makefile | 0bac5111 Sun Sep 23 12:51:25 CDT 2007 David Woodhouse <dwmw2@infradead.org> [MTD] map driver for NOR flash on the Intel Vermilion Range chipset
The Vermilion Range Expansion Bus supports four chip selects, each of which
has 64MiB of address space. The 2nd BAR of the Expansion Bus PCI Device
is a 256MiB memory region containing the address spaces for all four of
the chip selects, with start addresses hardcoded on 64MiB boundaries.
This map driver only supports NOR flash on chip select 0. The buswidth
(either 8 bits or 16 bits) is determined by reading the Expansion Bus Timing
and Control Register for Chip Select 0 (EXP_TIMING_CS0).
Signed-off-by: Andy Lowe <alowe@mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
0bac5111 Sun Sep 23 12:51:25 CDT 2007 David Woodhouse <dwmw2@infradead.org> [MTD] map driver for NOR flash on the Intel Vermilion Range chipset
The Vermilion Range Expansion Bus supports four chip selects, each of which
has 64MiB of address space. The 2nd BAR of the Expansion Bus PCI Device
is a 256MiB memory region containing the address spaces for all four of
the chip selects, with start addresses hardcoded on 64MiB boundaries.
This map driver only supports NOR flash on chip select 0. The buswidth
(either 8 bits or 16 bits) is determined by reading the Expansion Bus Timing
and Control Register for Chip Select 0 (EXP_TIMING_CS0).
Signed-off-by: Andy Lowe <alowe@mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
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| H A D | Kconfig | 0bac5111 Sun Sep 23 12:51:25 CDT 2007 David Woodhouse <dwmw2@infradead.org> [MTD] map driver for NOR flash on the Intel Vermilion Range chipset
The Vermilion Range Expansion Bus supports four chip selects, each of which
has 64MiB of address space. The 2nd BAR of the Expansion Bus PCI Device
is a 256MiB memory region containing the address spaces for all four of
the chip selects, with start addresses hardcoded on 64MiB boundaries.
This map driver only supports NOR flash on chip select 0. The buswidth
(either 8 bits or 16 bits) is determined by reading the Expansion Bus Timing
and Control Register for Chip Select 0 (EXP_TIMING_CS0).
Signed-off-by: Andy Lowe <alowe@mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
0bac5111 Sun Sep 23 12:51:25 CDT 2007 David Woodhouse <dwmw2@infradead.org> [MTD] map driver for NOR flash on the Intel Vermilion Range chipset
The Vermilion Range Expansion Bus supports four chip selects, each of which
has 64MiB of address space. The 2nd BAR of the Expansion Bus PCI Device
is a 256MiB memory region containing the address spaces for all four of
the chip selects, with start addresses hardcoded on 64MiB boundaries.
This map driver only supports NOR flash on chip select 0. The buswidth
(either 8 bits or 16 bits) is determined by reading the Expansion Bus Timing
and Control Register for Chip Select 0 (EXP_TIMING_CS0).
Signed-off-by: Andy Lowe <alowe@mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
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