Searched hist:"0 ae99b5f" (Results 1 – 3 of 3) sorted by relevance
/openbmc/linux/arch/mips/bcm63xx/ |
H A D | dev-enet.c | 0ae99b5f Tue Jun 04 16:53:34 CDT 2013 Maxime Bizon <mbizon@freebox.fr> bcm63xx_enet: split DMA channel register accesses
The current bcm63xx_enet driver always uses bcmenet_shared_base whenever it needs to access DMA channel configuration space or access the DMA channel state RAM. Split these register in 3 parts to be more accurate:
- global DMA configuration - per DMA channel configuration space - per DMA channel state RAM space
This is preliminary to support new chips where the global DMA configuration remains the same, but there is a varying number of DMA channels located at a different memory offset.
Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: David S. Miller <davem@davemloft.net> 0ae99b5f Tue Jun 04 16:53:34 CDT 2013 Maxime Bizon <mbizon@freebox.fr> bcm63xx_enet: split DMA channel register accesses The current bcm63xx_enet driver always uses bcmenet_shared_base whenever it needs to access DMA channel configuration space or access the DMA channel state RAM. Split these register in 3 parts to be more accurate: - global DMA configuration - per DMA channel configuration space - per DMA channel state RAM space This is preliminary to support new chips where the global DMA configuration remains the same, but there is a varying number of DMA channels located at a different memory offset. Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: David S. Miller <davem@davemloft.net>
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/openbmc/linux/arch/mips/include/asm/mach-bcm63xx/ |
H A D | bcm63xx_cpu.h | 0ae99b5f Tue Jun 04 16:53:34 CDT 2013 Maxime Bizon <mbizon@freebox.fr> bcm63xx_enet: split DMA channel register accesses
The current bcm63xx_enet driver always uses bcmenet_shared_base whenever it needs to access DMA channel configuration space or access the DMA channel state RAM. Split these register in 3 parts to be more accurate:
- global DMA configuration - per DMA channel configuration space - per DMA channel state RAM space
This is preliminary to support new chips where the global DMA configuration remains the same, but there is a varying number of DMA channels located at a different memory offset.
Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: David S. Miller <davem@davemloft.net> 0ae99b5f Tue Jun 04 16:53:34 CDT 2013 Maxime Bizon <mbizon@freebox.fr> bcm63xx_enet: split DMA channel register accesses The current bcm63xx_enet driver always uses bcmenet_shared_base whenever it needs to access DMA channel configuration space or access the DMA channel state RAM. Split these register in 3 parts to be more accurate: - global DMA configuration - per DMA channel configuration space - per DMA channel state RAM space This is preliminary to support new chips where the global DMA configuration remains the same, but there is a varying number of DMA channels located at a different memory offset. Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: David S. Miller <davem@davemloft.net>
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/openbmc/linux/drivers/net/ethernet/broadcom/ |
H A D | bcm63xx_enet.c | 0ae99b5f Tue Jun 04 16:53:34 CDT 2013 Maxime Bizon <mbizon@freebox.fr> bcm63xx_enet: split DMA channel register accesses
The current bcm63xx_enet driver always uses bcmenet_shared_base whenever it needs to access DMA channel configuration space or access the DMA channel state RAM. Split these register in 3 parts to be more accurate:
- global DMA configuration - per DMA channel configuration space - per DMA channel state RAM space
This is preliminary to support new chips where the global DMA configuration remains the same, but there is a varying number of DMA channels located at a different memory offset.
Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: David S. Miller <davem@davemloft.net> 0ae99b5f Tue Jun 04 16:53:34 CDT 2013 Maxime Bizon <mbizon@freebox.fr> bcm63xx_enet: split DMA channel register accesses The current bcm63xx_enet driver always uses bcmenet_shared_base whenever it needs to access DMA channel configuration space or access the DMA channel state RAM. Split these register in 3 parts to be more accurate: - global DMA configuration - per DMA channel configuration space - per DMA channel state RAM space This is preliminary to support new chips where the global DMA configuration remains the same, but there is a varying number of DMA channels located at a different memory offset. Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: David S. Miller <davem@davemloft.net>
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