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| H A D | sirfstar.yaml | 094b10cb Thu Mar 17 17:58:43 CDT 2022 Linus Walleij <linus.walleij@linaro.org> dt-bindings: gnss: Add two more chips
The CSR GSD4t is a CSR product using the SiRFstarIV core, and
the CSR CSRG05TA03-ICJE-R is a CSR product using the SiRFstarV
core.
These chips have a SRESETN line that can be pulled low to hard
reset the chip and in some designs this is connected to a GPIO,
so add this as an optional property.
Update the example with a reset line so users see that it need
to be tagged as active low.
Cc: devicetree@vger.kernel.org
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220317225844.1262643-4-linus.walleij@linaro.org
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