Searched hist:"075 cbae1" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | snps,hsdk-cgu.h | 075cbae1 Tue Jan 16 11:44:25 CST 2018 Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> ARC: HSDK: CGU: Update AXI, TUN, ARC clock options
Update default AXI, TUN, ARC clock set options:
instead of changing only IDIV divider settings adjust also domain PLL
settings.
Add support of TUN_ROM and TUN_PWM clocks (subclocks of TUNN_PLL)
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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| /openbmc/u-boot/drivers/clk/ |
| H A D | clk-hsdk-cgu.c | 075cbae1 Tue Jan 16 11:44:25 CST 2018 Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> ARC: HSDK: CGU: Update AXI, TUN, ARC clock options
Update default AXI, TUN, ARC clock set options:
instead of changing only IDIV divider settings adjust also domain PLL
settings.
Add support of TUN_ROM and TUN_PWM clocks (subclocks of TUNN_PLL)
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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