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H A D | wm8804.h | 06109f47 Thu May 29 09:08:03 CDT 2014 Daniel Matuschek <info@crazy-audio.com> ASoC: wm8804: Allow control of master clock divider in PLL generation
WM8804 can run with PLL frequencies of 256xfs and 128xfs for most sample rates. At 192kHz only 128xfs is supported. The existing driver selects 128xfs automatically for some lower samples rates. By using an additional mclk_div divider, it is now possible to control the behaviour. This allows using 256xfs PLL frequency on all sample rates up to 96kHz. It should allow lower jitter and better signal quality. The behavior has to be controlled by the sound card driver, because some sample frequency share the same setting. e.g. 192kHz and 96kHz use 24.576MHz master clock. The only difference is the MCLK divider.
Signed-off-by: Daniel Matuschek <daniel@matuschek.net> Tested-by: Florian Meier <florian.meier@koalo.de> Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Mark Brown <broonie@linaro.org> 06109f47 Thu May 29 09:08:03 CDT 2014 Daniel Matuschek <info@crazy-audio.com> ASoC: wm8804: Allow control of master clock divider in PLL generation WM8804 can run with PLL frequencies of 256xfs and 128xfs for most sample rates. At 192kHz only 128xfs is supported. The existing driver selects 128xfs automatically for some lower samples rates. By using an additional mclk_div divider, it is now possible to control the behaviour. This allows using 256xfs PLL frequency on all sample rates up to 96kHz. It should allow lower jitter and better signal quality. The behavior has to be controlled by the sound card driver, because some sample frequency share the same setting. e.g. 192kHz and 96kHz use 24.576MHz master clock. The only difference is the MCLK divider. Signed-off-by: Daniel Matuschek <daniel@matuschek.net> Tested-by: Florian Meier <florian.meier@koalo.de> Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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H A D | wm8804.c | 06109f47 Thu May 29 09:08:03 CDT 2014 Daniel Matuschek <info@crazy-audio.com> ASoC: wm8804: Allow control of master clock divider in PLL generation
WM8804 can run with PLL frequencies of 256xfs and 128xfs for most sample rates. At 192kHz only 128xfs is supported. The existing driver selects 128xfs automatically for some lower samples rates. By using an additional mclk_div divider, it is now possible to control the behaviour. This allows using 256xfs PLL frequency on all sample rates up to 96kHz. It should allow lower jitter and better signal quality. The behavior has to be controlled by the sound card driver, because some sample frequency share the same setting. e.g. 192kHz and 96kHz use 24.576MHz master clock. The only difference is the MCLK divider.
Signed-off-by: Daniel Matuschek <daniel@matuschek.net> Tested-by: Florian Meier <florian.meier@koalo.de> Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Mark Brown <broonie@linaro.org> 06109f47 Thu May 29 09:08:03 CDT 2014 Daniel Matuschek <info@crazy-audio.com> ASoC: wm8804: Allow control of master clock divider in PLL generation WM8804 can run with PLL frequencies of 256xfs and 128xfs for most sample rates. At 192kHz only 128xfs is supported. The existing driver selects 128xfs automatically for some lower samples rates. By using an additional mclk_div divider, it is now possible to control the behaviour. This allows using 256xfs PLL frequency on all sample rates up to 96kHz. It should allow lower jitter and better signal quality. The behavior has to be controlled by the sound card driver, because some sample frequency share the same setting. e.g. 192kHz and 96kHz use 24.576MHz master clock. The only difference is the MCLK divider. Signed-off-by: Daniel Matuschek <daniel@matuschek.net> Tested-by: Florian Meier <florian.meier@koalo.de> Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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