Searched hist:"05 b98ec3" (Results 1 – 6 of 6) sorted by relevance
| /openbmc/u-boot/arch/x86/include/asm/arch-quark/ |
| H A D | device.h | 05b98ec3 Mon May 25 09:35:06 CDT 2015 Bin Meng <bmeng.cn@gmail.com> x86: quark: Implement PIRQ routing
Intel Quark SoC has the same interrupt routing mechanism as the
Queensbay platform, only the difference is that PCI devices'
INTA/B/C/D are harcoded and cannot be changed freely.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
|
| H A D | quark.h | 05b98ec3 Mon May 25 09:35:06 CDT 2015 Bin Meng <bmeng.cn@gmail.com> x86: quark: Implement PIRQ routing
Intel Quark SoC has the same interrupt routing mechanism as the
Queensbay platform, only the difference is that PCI devices'
INTA/B/C/D are harcoded and cannot be changed freely.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
|
| /openbmc/u-boot/arch/x86/dts/ |
| H A D | galileo.dts | 05b98ec3 Mon May 25 09:35:06 CDT 2015 Bin Meng <bmeng.cn@gmail.com> x86: quark: Implement PIRQ routing
Intel Quark SoC has the same interrupt routing mechanism as the
Queensbay platform, only the difference is that PCI devices'
INTA/B/C/D are harcoded and cannot be changed freely.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
|
| /openbmc/u-boot/include/configs/ |
| H A D | galileo.h | 05b98ec3 Mon May 25 09:35:06 CDT 2015 Bin Meng <bmeng.cn@gmail.com> x86: quark: Implement PIRQ routing
Intel Quark SoC has the same interrupt routing mechanism as the
Queensbay platform, only the difference is that PCI devices'
INTA/B/C/D are harcoded and cannot be changed freely.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
|
| /openbmc/u-boot/arch/x86/cpu/quark/ |
| H A D | quark.c | 05b98ec3 Mon May 25 09:35:06 CDT 2015 Bin Meng <bmeng.cn@gmail.com> x86: quark: Implement PIRQ routing
Intel Quark SoC has the same interrupt routing mechanism as the
Queensbay platform, only the difference is that PCI devices'
INTA/B/C/D are harcoded and cannot be changed freely.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
|
| /openbmc/u-boot/configs/ |
| H A D | galileo_defconfig | 05b98ec3 Mon May 25 09:35:06 CDT 2015 Bin Meng <bmeng.cn@gmail.com> x86: quark: Implement PIRQ routing
Intel Quark SoC has the same interrupt routing mechanism as the
Queensbay platform, only the difference is that PCI devices'
INTA/B/C/D are harcoded and cannot be changed freely.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
|