Searched hist:"043715 d1" (Results 1 – 4 of 4) sorted by relevance
| /openbmc/qemu/include/hw/misc/ |
| H A D | mips_itu.h | 043715d1 Thu Jan 03 09:46:32 CST 2019 Yongbok Kim <yongbok.kim@mips.com> target/mips: Update ITU to utilize SAARI and SAAR CP0 registers
Update ITU to utilize SAARI and SAAR CP0 registers.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
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| /openbmc/qemu/hw/misc/ |
| H A D | mips_itu.c | 043715d1 Thu Jan 03 09:46:32 CST 2019 Yongbok Kim <yongbok.kim@mips.com> target/mips: Update ITU to utilize SAARI and SAAR CP0 registers
Update ITU to utilize SAARI and SAAR CP0 registers.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
|
| /openbmc/qemu/hw/mips/ |
| H A D | cps.c | 043715d1 Thu Jan 03 09:46:32 CST 2019 Yongbok Kim <yongbok.kim@mips.com> target/mips: Update ITU to utilize SAARI and SAAR CP0 registers
Update ITU to utilize SAARI and SAAR CP0 registers.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
|
| /openbmc/qemu/target/mips/ |
| H A D | cpu.h | 043715d1 Thu Jan 03 09:46:32 CST 2019 Yongbok Kim <yongbok.kim@mips.com> target/mips: Update ITU to utilize SAARI and SAAR CP0 registers
Update ITU to utilize SAARI and SAAR CP0 registers.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
|