Searched hist:"040 e165b" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/drivers/clk/meson/ |
| H A D | meson8b.h | 040e165b Tue Jul 13 18:25:08 CDT 2021 Martin Blumenstingl <martin.blumenstingl@googlemail.com> clk: meson: meson8b: Initialize the HDMI PLL registers
Add the reg_sequence to initialize the HDMI PLL with the settings for
a video mode that doesn't require PLL internal clock doubling. These
settings are taken from the 3.10 vendor kernel's driver for the 2970MHz
PLL setting used for the 1080P video mode. This puts the PLL into a
defined state and the Linux kernel can take over.
While not all bits for this PLL are implemented using these "defaults"
and then applying M, N and FRAC seems to work fine.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20210713232510.3057750-5-martin.blumenstingl@googlemail.com
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| H A D | meson8b.c | 040e165b Tue Jul 13 18:25:08 CDT 2021 Martin Blumenstingl <martin.blumenstingl@googlemail.com> clk: meson: meson8b: Initialize the HDMI PLL registers
Add the reg_sequence to initialize the HDMI PLL with the settings for
a video mode that doesn't require PLL internal clock doubling. These
settings are taken from the 3.10 vendor kernel's driver for the 2970MHz
PLL setting used for the 1080P video mode. This puts the PLL into a
defined state and the Linux kernel can take over.
While not all bits for this PLL are implemented using these "defaults"
and then applying M, N and FRAC seems to work fine.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20210713232510.3057750-5-martin.blumenstingl@googlemail.com
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