Searched hist:"000 b99e5" (Results 1 – 3 of 3) sorted by relevance
| /openbmc/linux/arch/arm64/boot/dts/nvidia/ |
| H A D | tegra234.dtsi | 000b99e5 Tue Apr 26 02:38:27 CDT 2022 Ashish Mhetre <amhetre@nvidia.com> arm64: tegra: Add memory controller channels
From tegra186 onwards, memory controller support multiple channels.
During the error interrupts from memory controller, corresponding
channels need to be accessed for logging error info and clearing the
interrupt.
So add address and size of these channels in device tree node of
tegra186, tegra194 and tegra234 memory controller. Also add reg-names
for each of these reg items which are used by driver for mapping.
Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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| H A D | tegra186.dtsi | 000b99e5 Tue Apr 26 02:38:27 CDT 2022 Ashish Mhetre <amhetre@nvidia.com> arm64: tegra: Add memory controller channels
From tegra186 onwards, memory controller support multiple channels.
During the error interrupts from memory controller, corresponding
channels need to be accessed for logging error info and clearing the
interrupt.
So add address and size of these channels in device tree node of
tegra186, tegra194 and tegra234 memory controller. Also add reg-names
for each of these reg items which are used by driver for mapping.
Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| H A D | tegra194.dtsi | 000b99e5 Tue Apr 26 02:38:27 CDT 2022 Ashish Mhetre <amhetre@nvidia.com> arm64: tegra: Add memory controller channels
From tegra186 onwards, memory controller support multiple channels.
During the error interrupts from memory controller, corresponding
channels need to be accessed for logging error info and clearing the
interrupt.
So add address and size of these channels in device tree node of
tegra186, tegra194 and tegra234 memory controller. Also add reg-names
for each of these reg items which are used by driver for mapping.
Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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