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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dxlnx,xps-timer.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/timer/xlnx,xps-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx LogiCORE IP AXI Timer
10 - Sean Anderson <sean.anderson@seco.com>
15 const: xlnx,xps-timer-1.00.a
18 maxItems: 1
20 clock-names:
24 maxItems: 1
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/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dxlnx,xps-timebase-wdt.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/watchdog/xlnx,xps-timebase-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx AXI/PLB softcore and window Watchdog Timer
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11 - Srinivas Neeli <srinivas.neeli@amd.com>
14 The Timebase watchdog timer(WDT) is a free-running 32 bit counter.
15 WDT uses a dual-expiration architecture. After one expiration of
22 - $ref: watchdog.yaml#
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/openbmc/linux/arch/microblaze/boot/dts/
H A Dsystem.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * (C) Copyright 2007-2008 Xilinx, Inc.
6 * (C) Copyright 2007-2009 Michal Simek
13 * XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101
16 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
32 stdout-path = "/plb@0/serial@84000000";
35 #address-cells = <1>;
37 #size-cells = <0>;
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/openbmc/qemu/hw/microblaze/
H A Dpetalogix_s3adsp1800_mmu.c2 * Model of Petalogix linux reference design targeting Xilinx Spartan 3ADSP-1800
36 #include "exec/address-spaces.h"
44 #define BINARY_DEVICE_TREE_FILE "petalogix-s3adsp1800.dtb"
55 #define ETHLITE_IRQ 1
59 MACHINE_TYPE_NAME("petalogix-s3adsp1800")
64 ram_addr_t ram_size = machine->ram_size; in petalogix_s3adsp1800_init()
70 MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1); in petalogix_s3adsp1800_init()
71 MemoryRegion *phys_ram = g_new(MemoryRegion, 1); in petalogix_s3adsp1800_init()
77 object_property_set_bool(OBJECT(cpu), "little-endian", in petalogix_s3adsp1800_init()
95 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1); in petalogix_s3adsp1800_init()
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H A Dpetalogix_ml605_mmu.c37 #include "hw/char/serial-mm.h"
38 #include "hw/qdev-properties.h"
39 #include "exec/address-spaces.h"
49 #define BINARY_DEVICE_TREE_FILE "petalogix-ml605.dtb"
63 #define AXIDMA_IRQ0 1
72 ram_addr_t ram_size = machine->ram_size; in petalogix_ml605_init()
80 MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1); in petalogix_ml605_init()
81 MemoryRegion *phys_ram = g_new(MemoryRegion, 1); in petalogix_ml605_init()
90 object_property_set_int(OBJECT(cpu), "use-fpu", 1, &error_abort); in petalogix_ml605_init()
91 object_property_set_bool(OBJECT(cpu), "dcache-writeback", true, in petalogix_ml605_init()
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/openbmc/qemu/pc-bios/
H A Dpetalogix-s3adsp1800.dts5 * SPDX-License-Identifier: GPL-2.0+
8 /dts-v1/;
11 #address-cells = <0x01>;
12 #size-cells = <0x01>;
23 stdout-path = "/plb/serial@84000000";
27 #address-cells = <0x01>;
28 #size-cells = <0x00>;
32 clock-frequency = <0x3b9aca0>;
33 compatible = "xlnx,microblaze-7.10.d";
34 d-cache-baseaddr = <0x90000000>;
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H A Dpetalogix-ml605.dts5 * SPDX-License-Identifier: GPL-2.0+
8 /dts-v1/;
11 #address-cells = < 0x01 >;
12 #size-cells = < 0x01 >;
22 ethernet0 = "/axi/axi-ethernet@82780000";
28 stdout-path = "/axi/serial@83e00000";
32 #address-cells = < 0x01 >;
34 #size-cells = < 0x00 >;
37 clock-frequency = < 0xbebc200 >;
38 compatible = "xlnx,microblaze-8.10.a";
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/openbmc/u-boot/drivers/watchdog/
H A Dxilinx_tb_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Xilinx AXI platforms watchdog timer driver.
8 * Copyright (c) 2011-2018 Xilinx Inc.
17 #define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state Mask */
18 #define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 Mask*/
40 reg = readl(&platdata->regs->twcsr0); in xlnx_wdt_reset()
44 writel(reg | XWT_CSR0_WDS_MASK, &platdata->regs->twcsr0); in xlnx_wdt_reset()
54 if (platdata->enable_once) { in xlnx_wdt_stop()
56 return -EBUSY; in xlnx_wdt_stop()
60 reg = readl(&platdata->regs->twcsr0); in xlnx_wdt_stop()
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/openbmc/qemu/hw/timer/
H A Dxilinx_timer.c2 * QEMU model of the Xilinx timer block.
29 #include "hw/qdev-properties.h"
37 #define R_TLR 1
41 #define TCSR_MDT (1<<0)
42 #define TCSR_UDT (1<<1)
43 #define TCSR_GENT (1<<2)
44 #define TCSR_CAPT (1<<3)
45 #define TCSR_ARHT (1<<4)
46 #define TCSR_LOAD (1<<5)
47 #define TCSR_ENIT (1<<6)
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/openbmc/u-boot/arch/microblaze/cpu/
H A Dtimer.c1 // SPDX-License-Identifier: GPL-2.0+
21 return timestamp - base; in get_timer()
22 return timestamp++ - base; in get_timer()
31 while ((get_timer(0) - i) < (usec / 1000)) in __udelay()
40 tmr->control = tmr->control | TIMER_INTERRUPT; in timer_isr()
45 int irq = -1; in timer_init()
48 const void *blob = gd->fdt_blob; in timer_init()
52 debug("TIMER: Initialization\n"); in timer_init()
55 if (!(gd->flags & GD_FLG_RELOC)) in timer_init()
59 "xlnx,xps-timer-1.00.a"); in timer_init()
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/openbmc/linux/drivers/watchdog/
H A Dof_xilinx_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2013 - 2014 Xilinx, Inc.
28 #define XWT_CSR0_WDS_MASK BIT(2) /* Timer state */
29 #define XWT_CSR0_EWDT1_MASK BIT(1) /* Enable bit 1 */
31 /* Control/Status Register 0/1 bits */
54 ret = clk_enable(xdev->clk); in xilinx_wdt_start()
56 dev_err(wdd->parent, "Failed to enable clock\n"); in xilinx_wdt_start()
60 spin_lock(&xdev->spinlock); in xilinx_wdt_start()
62 /* Clean previous status and enable the watchdog timer */ in xilinx_wdt_start()
63 control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); in xilinx_wdt_start()
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/openbmc/linux/net/sunrpc/
H A Dxprt.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * - When a process places a call, it allocates a request slot if
13 * - Next, the caller puts together the RPC message, stuffs it into
15 * - xprt_transmit sends the message and installs the caller on the
17 * it installs a timer that is run after the packet's timeout has
19 * - When a packet arrives, the data_ready handler walks the list of
21 * caller is woken up, and the timer removed.
22 * - When no reply arrives within the timeout interval, the timer is
25 * of -ETIMEDOUT.
26 * - When the caller receives a notification from RPC that a reply arrived,
[all …]
/openbmc/qemu/hw/ppc/
H A Dvirtex_ml507.c2 * Model of Xilinx Virtex5 ML507 PPC-440 refdesign.
28 #include "exec/page-protection.h"
31 #include "hw/char/serial-mm.h"
40 #include "qemu/error-report.h"
43 #include "hw/intc/ppc-uic.h"
46 #include "hw/qdev-properties.h"
78 env = &cpu->env; in ppc440_init_xilinx()
101 CPUPPCState *env = &cpu->env; in main_cpu_reset()
102 struct boot_info *bi = env->load_info; in main_cpu_reset()
114 env->gpr[1] = (16 * MiB) - 8; in main_cpu_reset()
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/openbmc/linux/arch/sh/boot/dts/
H A Dj2_mimas_v2.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 compatible = "jcore,j2-soc";
8 #address-cells = <1>;
9 #size-cells = <1>;
11 interrupt-parent = <&aic>;
14 #address-cells = <1>;
15 #size-cells = <0>;
21 clock-frequency = <50000000>;
22 d-cache-size = <8192>;
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/openbmc/linux/arch/microblaze/kernel/
H A Dtimer.c2 * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2012-2013 Xilinx, Inc.
4 * Copyright (C) 2007-2009 PetaLogix
36 #define TCSR_MDT (1<<0)
37 #define TCSR_UDT (1<<1)
38 #define TCSR_GENT (1<<2)
39 #define TCSR_CAPT (1<<3)
40 #define TCSR_ARHT (1<<4)
41 #define TCSR_LOAD (1<<5)
42 #define TCSR_ENIT (1<<6)
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/openbmc/linux/include/linux/sunrpc/
H A Dxprt.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 #define RPC_CWNDSCALE (1U << RPC_CWNDSHIFT)
30 #define RPC_MAXCWND(xprt) ((xprt)->max_reqs << RPC_CWNDSHIFT)
31 #define RPCXPRT_CONGESTED(xprt) ((xprt)->cong >= (xprt)->cwnd)
66 * This is the user-visible part
78 int rq_cong; /* has incremented xprt->cong */
107 ktime_t rq_rtt; /* round-trip time */
166 void (*timer)(struct rpc_xprt *xprt, struct rpc_task *task); member
195 #define XPRT_TRANSPORT_BC (1 << 31)
232 unsigned char resvport : 1, /* use a reserved port */
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H A Dclnt.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Declarations for the high-level RPC client interface
25 #include <linux/sunrpc/timer.h>
42 * The high-level client handle
58 struct rpc_stat * cl_stats; /* per-program statistics */
59 struct rpc_iostats * cl_metrics; /* per-client statistics */
61 unsigned int cl_softrtry : 1,/* soft timeouts */
62 cl_softerr : 1,/* Timeouts return errors */
63 cl_discrtry : 1,/* disconnect before retry */
64 cl_noretranstimeo: 1,/* No retransmit timeouts */
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/openbmc/linux/drivers/input/serio/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
113 This driver provides support for the PS/2 ports on PA-RISC machines
130 The SDC itself contains a 10ms resolution timer/clock capable
131 of delivering interrupts on a periodic and one-shot basis.
132 The SDC may also be connected to a battery-backed real-time
133 clock, a basic audio waveform generator, and an HP-HIL Master
196 allocating minor 1 (that historically corresponds to /dev/psaux)
199 echo -n "serio_raw" > /sys/bus/serio/devices/serioX/drvctl
205 tristate "Xilinx XPS PS/2 Controller Support"
208 This driver supports XPS PS/2 IP from the Xilinx EDK on
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/openbmc/linux/drivers/pwm/
H A Dpwm-xilinx.c1 // SPDX-License-Identifier: GPL-2.0+
6 * - When changing both duty cycle and period, we may end up with one cycle
13 * - Cannot produce 100% duty cycle by configuring the TLRs. This might be
16 * - Only produces "normal" output.
17 * - Always produces low output if disabled.
20 #include <clocksource/timer-xilinx.h>
22 #include <linux/clk-provider.h>
37 WARN_ON(cycles < 2 || cycles - 2 > priv->max); in xilinx_timer_tlr_cycles()
40 return cycles - 2; in xilinx_timer_tlr_cycles()
41 return priv->max - cycles + 2; in xilinx_timer_tlr_cycles()
[all …]
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gt_clock_utils.c1 // SPDX-License-Identifier: MIT
19 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1; in read_reference_ts_freq()
25 frac_freq = 1000000 / (frac_freq + 1); in read_reference_ts_freq()
82 freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> in gen11_read_clock_frequency()
97 freq = IS_GEN9_LP(uncore->i915) ? 19200000 : 24000000; in gen9_read_clock_frequency()
104 freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >> in gen9_read_clock_frequency()
135 * 63:20 increments every 1/4 ns in g4x_read_clock_frequency()
138 * -> 63:32 increments every 1024 ns in g4x_read_clock_frequency()
154 return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000; in gen4_read_clock_frequency()
159 if (GRAPHICS_VER(uncore->i915) >= 11) in read_clock_frequency()
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/openbmc/linux/drivers/char/xilinx_hwicap/
H A Dxilinx_hwicap.c26 * (c) Copyright 2007-2008 Xilinx Inc.
36 * This is the code behind /dev/icap* -- it allows a user-space
64 * user-space application code that uses this device. The simplest
109 #define HWICAP_DEVICES 1
124 .FAR = 1,
142 .TIMER = UNIMPLEMENTED,
149 .FAR = 1,
167 .TIMER = UNIMPLEMENTED,
174 .FAR = 1,
192 .TIMER = 17,
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/openbmc/linux/arch/x86/kernel/
H A Dapm_32.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* -*- linux-c -*-
4 * Copyright 1994-2001 Stephen Rothwell (sfr@canb.auug.org.au)
16 * (Thanks to Ulrich Windl <Ulrich.Windl@rz.uni-regensburg.de>)
43 * 1.1: support user-space standby and suspend, power off after system
46 * is only incorrect by 30-60mS (vs. 1S previously) (Gabor J. Toth
48 * screen-blanking and gpm (Stephen Rothwell); Linux 1.99.4
63 * <echter@informatik.uni-rostock.de>
68 * Reset interrupt 0 timer to 100Hz after suspend
109 * <Walter.Hofmann@physik.stud.uni-erlangen.de>).
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/openbmc/linux/net/sched/
H A Dsch_fq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2013-2015 Eric Dumazet <edumazet@google.com>
8 * Fast classification depends on skb->sk being set before reaching us.
17 * Transport (eg TCP) can set in sk->sk_pacing_rate a rate, enqueue a
22 * - lookup one RB tree (out of 1024 or more) to find the flow.
25 * - Use a special fifo for high prio packets
60 return (struct fq_skb_cb *)qdisc_skb_cb(skb)->data; in fq_skb_cb()
65 * If packets have monotically increasing time_to_send, they are placed in O(1)
74 unsigned long age; /* (jiffies | 1UL) when flow was emptied, for gc */
87 struct rb_node rate_node; /* anchor in q->delayed tree */
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/openbmc/linux/include/linux/
H A Dnetdevice.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 * Corey Minyard <wf-rch!minyard@relay.EU.net>
24 #include <linux/timer.h>
54 #include <net/dropreason-core.h>
92 #define NET_RX_DROP 1 /* packet dropped */
100 * - qdisc return codes
101 * - driver transmit return codes
102 * - errno values
106 * the driver transmit return codes though - when qdiscs are used, the actual
113 /* qdisc ->enqueue() return codes. */
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/openbmc/linux/drivers/net/ethernet/intel/fm10k/
H A Dfm10k_pci.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2019 Intel Corporation. */
15 * fm10k_pci_tbl - PCI Device ID Table
35 struct fm10k_intfc *interface = hw->back; in fm10k_read_pci_cfg_word()
38 if (FM10K_REMOVED(hw->hw_addr)) in fm10k_read_pci_cfg_word()
41 pci_read_config_word(interface->pdev, reg, &value); in fm10k_read_pci_cfg_word()
50 u32 __iomem *hw_addr = READ_ONCE(hw->hw_addr); in fm10k_read_reg()
58 struct fm10k_intfc *interface = hw->back; in fm10k_read_reg()
59 struct net_device *netdev = interface->netdev; in fm10k_read_reg()
61 hw->hw_addr = NULL; in fm10k_read_reg()
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