Searched +full:xps +full:- +full:ethernetlite +full:- +full:3 (Results 1 – 4 of 4) sorted by relevance
2 * Model of Petalogix linux reference design targeting Xilinx Spartan 3ADSP-180036 #include "exec/address-spaces.h"44 #define BINARY_DEVICE_TREE_FILE "petalogix-s3adsp1800.dtb"56 #define UARTLITE_IRQ 359 MACHINE_TYPE_NAME("petalogix-s3adsp1800")64 ram_addr_t ram_size = machine->ram_size; in petalogix_s3adsp1800_init()77 object_property_set_bool(OBJECT(cpu), "little-endian", in petalogix_s3adsp1800_init()97 dev = qdev_new("xlnx.xps-intc"); in petalogix_s3adsp1800_init()98 qdev_prop_set_uint32(dev, "kind-of-intr", in petalogix_s3adsp1800_init()115 dev = qdev_new("xlnx.xps-timer"); in petalogix_s3adsp1800_init()[all …]
5 * SPDX-License-Identifier: GPL-2.0+8 /dts-v1/;11 #address-cells = <0x01>;12 #size-cells = <0x01>;23 stdout-path = "/plb/serial@84000000";27 #address-cells = <0x01>;28 #size-cells = <0x00>;32 clock-frequency = <0x3b9aca0>;33 compatible = "xlnx,microblaze-7.10.d";34 d-cache-baseaddr = <0x90000000>;[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later7 * Copyright (c) 2007 - 2013 Xilinx, Inc.104 * struct net_local - Our private per device data144 * xemaclite_enable_interrupts - Enable the interrupts for the EmacLite device155 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET); in xemaclite_enable_interrupts()157 drvdata->base_addr + XEL_TSR_OFFSET); in xemaclite_enable_interrupts()160 xemaclite_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET); in xemaclite_enable_interrupts()163 xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET); in xemaclite_enable_interrupts()167 * xemaclite_disable_interrupts - Disable the interrupts for the EmacLite device178 xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET); in xemaclite_disable_interrupts()[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * (C) Copyright 2007-2009 Michal Simek64 u32 tx_ping; /* 0x0 - TX Ping buffer */66 u32 mdioaddr; /* 0x7e4 - MDIO Address Register */67 u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */68 u32 mdiord;/* 0x7ec - MDIO Read Data Register */69 u32 mdioctrl; /* 0x7f0 - MDIO Control Register */70 u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */71 u32 global_interrupt; /* 0x7f8 - Global interrupt enable */72 u32 tx_ping_tsr; /* 0x7fc - Tx status */[all …]