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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti,gpmc-child.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
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/openbmc/linux/arch/x86/kernel/acpi/
H A Dboot.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * boot.c - Architecture-Specific Low-Level ACPI Boot Support
22 #include <linux/efi-bgrt.h>
80 * ->device_hotplug_lock
81 * ->acpi_ioapic_lock
82 * ->ioapic_lock
84 * ->acpi_ioapic_lock
85 * ->ioapic_mutex
86 * ->ioapic_lock
91 /* --------------------------------------------------------------------------
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/openbmc/linux/drivers/auxdisplay/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
4 # see Documentation/kbuild/kconfig-language.rst.
22 This is the base system for character-based LCD displays.
31 This is the core support for single-line character displays, to be
66 and built-in as well (Y).
100 Amount of time the ks0108 should wait between each control write
121 If you have a Crystalfontz 128x64 2-color LCD, cfag12864b Series,
125 check Documentation/admin-guide/auxdisplay/cfag12864b.rst
211 Say Y here if you have an HD44780 or KS-0074 LCD connected to your
212 parallel port. This driver also features 4 and 6-key keypads. The LCD
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/openbmc/linux/include/linux/
H A Dwm97xx.h1 /* SPDX-License-Identifier: GPL-2.0 */
62 #define WM97XX_SLT(i) ((i - 5) & 0x7) /* panel slot (5-11) */
71 #define WM9712_45W 0x1000 /* set for 5-wire touchscreen */
73 #define WM9712_WAIT 0x0200 /* wait until adc is read before next sample */
75 #define WM9712_MASK_HI 0x0040 /* hi on mask pin (47) stops conversions */
76 #define WM9712_MASK_EDGE 0x0080 /* rising/falling edge on pin delays sample */
90 #define WM9705_WAIT 0x0100 /* wait until adc is read before next sample */
94 #define WM9705_MASK_EDGE 0x0020 /* rising/falling edge on pin delays sample */
100 #define WM9713_PDPOL 0x0400 /* Pen down polarity */
110 #define WM9713_WAIT 0x0200 /* coordinate wait */
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/openbmc/linux/include/linux/platform_data/
H A Dgpmc-omap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
59 u32 access; /* Start-cycle to first data valid delay */
134 #define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */
135 #define GPMC_DEVWIDTH_16BIT 2 /* 16-bit device width */
136 #define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */
137 #define GPMC_MUX_AD 2 /* Addr-Data multiplex */
139 /* Wait pin polarity values */
153 bool wait_on_read; /* monitor wait on reads */
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/openbmc/linux/arch/m68k/include/asm/
H A DMC68328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68328.h: '328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
26 * 0xFFFFF0xx -- System Control
36 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
39 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
42 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
52 * 0xFFFFF1xx -- Chip-Select logic
58 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
76 #define GRPBASE_GBA_MASK 0xfff0 /* Group Base Address (bits 31-20) */
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H A DMC68EZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
27 * 0xFFFFF0xx -- System Control
37 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
40 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
43 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
53 * 0xFFFFF1xx -- Chip-Select logic
84 #define CSA_EN 0x0001 /* Chip-Select Enable */
85 #define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
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H A DMC68VZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
5 * Copyright (c) 2000-2001 Lineo Inc. <www.lineo.com>
6 * Copyright (c) 2000-2001 Lineo Canada Corp. <www.lineo.ca>
9 * Based on include/asm-m68knommu/MC68332.h
29 * 0xFFFFF0xx -- System Control
39 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
42 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
45 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
55 * 0xFFFFF1xx -- Chip-Select logic
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/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dcs35l36.txt5 - compatible : "cirrus,cs35l36"
7 - reg : the I2C address of the device for I2C
9 - VA-supply, VP-supply : power supplies for the device,
13 - cirrus,boost-ctl-millivolt : Boost Voltage Value. Configures the boost
18 - cirrus,boost-peak-milliamp : Boost-converter peak current limit in mA.
24 - cirrus,boost-ind-nanohenry : Inductor estimation LBST reference value.
32 - cirrus,multi-amp-mode : Boolean to determine if there are more than
33 one amplifier in the system. If more than one it is best to Hi-Z the ASP
36 - cirrus,boost-ctl-select : Boost converter control source selection.
39 0x00 - Control Port Value
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/openbmc/linux/include/linux/usb/
H A Dtcpm.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright 2015-2017 Google, Inc
31 /* Time to wait for TCPC to complete transmit */
56 #define TCPC_MUX_POLARITY_INVERTED BIT(2) /* Polarity inverted */
59 * struct tcpc_dev - Port configuration and callback functions
64 * and cc=Rp-def. This allows the tcpm to provide a fallback
65 * current-limit detection method for the cc=Rp-def case.
71 * @get_cc: Called to read current CC pin values
73 * Called to set polarity
82 * Optional; if supported by hardware, called to start dual-role
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/openbmc/linux/drivers/memory/
H A Domap-gpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
32 #include <linux/omap-gpmc.h>
36 #include <linux/platform_data/mtd-nand-omap2.h>
38 #define DEVICE_NAME "omap-gpmc"
137 #define GPMC_CONFIG_WAITPINPOLARITY(pin) (BIT(pin) << 8) argument
234 u32 pin; member
235 u32 polarity; member
257 /* Define chip-selects as reserved by default until probe completes */
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/openbmc/linux/drivers/video/fbdev/
H A Dpxa3xx-regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
73 #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome display */
74 #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome display */
90 #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
91 #define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL))
94 #define LCCR1_HorSnchWdth(Tpix) (((Tpix) - 1) << FShft (LCCR1_HSW))
96 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait - 1 */
97 #define LCCR1_EndLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_ELW))
99 #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
100 #define LCCR1_BegLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_BLW))
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/openbmc/u-boot/board/technexion/pico-imx6ul/
H A Dpico-imx6ul.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/mx6-pins.h>
15 #include <asm/mach-imx/iomux-v3.h>
73 * According to KSZ8081MNX-RNB manual: in board_eth_init()
74 * For warm reset, the reset (RST#) pin should be asserted low for a in board_eth_init()
75 * minimum of 500μs. The strap-in pin values are read and updated in board_eth_init()
76 * at the de-assertion of reset. in board_eth_init()
82 * According to KSZ8081MNX-RNB manual: in board_eth_init()
83 * After the de-assertion of reset, wait a minimum of 100μs before in board_eth_init()
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/openbmc/linux/drivers/net/ethernet/intel/e1000/
H A De1000_hw.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
13 e1000_rev_polarity *polarity);
89 * e1000_set_phy_type - Set the phy type member in the hw struct.
94 if (hw->mac_type == e1000_undefined) in e1000_set_phy_type()
95 return -E1000_ERR_PHY_TYPE; in e1000_set_phy_type()
97 switch (hw->phy_id) { in e1000_set_phy_type()
103 hw->phy_type = e1000_phy_m88; in e1000_set_phy_type()
106 if (hw->mac_type == e1000_82541 || in e1000_set_phy_type()
107 hw->mac_type == e1000_82541_rev_2 || in e1000_set_phy_type()
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/openbmc/linux/sound/soc/codecs/
H A Dtas6424.c1 // SPDX-License-Identifier: GPL-2.0
3 * ALSA SoC Texas Instruments TAS6424 Quad-Channel Audio Amplifier
5 * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
23 #include <sound/soc-dapm.h>
32 "dvdd", /* Digital power supply. Connect to 3.3-V supply. */
34 "pvdd", /* Class-D amp output FETs supply. */
52 * DAC digital volumes. From -103.5 to 24 dB in 0.5 dB steps. Note that
53 * setting the gain below -100 dB (register value <0x7) is effectively a MUTE
56 static DECLARE_TLV_DB_SCALE(dac_tlv, -10350, 50, 0);
74 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in tas6424_dac_event()
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/openbmc/linux/Documentation/devicetree/bindings/input/
H A Diqs269a.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 The Azoteq IQS269A is an 8-channel capacitive touch controller that features
14 additional Hall-effect and inductive sensing capabilities.
28 "#address-cells":
31 "#size-cells":
34 azoteq,hall-enable:
37 Enables Hall-effect sensing on channels 6 and 7. In this case, keycodes
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H A Diqs626a.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 The Azoteq IQS626A is a 14-channel capacitive touch controller that features
14 additional Hall-effect and inductive sensing capabilities.
19 - $ref: touchscreen/touchscreen.yaml#
31 "#address-cells":
34 "#size-cells":
37 azoteq,suspend-mode:
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/openbmc/linux/arch/x86/kernel/apic/
H A Dio_apic.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel IO-APIC support for multi-Pentium hosts.
10 * (c) 1999, Multiple IO-APIC support, developed by
11 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
25 * - SiS APIC rmw bug:
28 * required to rewrite the index register for a read-modify-write
74 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
75 #define for_each_pin(idx, pin) \ argument
76 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
77 #define for_each_ioapic_pin(idx, pin) \ argument
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/openbmc/linux/drivers/extcon/
H A Dextcon-usbc-tusb320.c1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/extcon/extcon-tusb320.c - TUSB320 extcon driver
10 #include <linux/extcon-provider.h>
107 ret = regmap_read(priv->regmap, sizeof(sig) - 1 - i, &val); in tusb320_check_signature()
111 dev_err(priv->dev, "signature mismatch!\n"); in tusb320_check_signature()
112 return -ENODEV; in tusb320_check_signature()
124 if (priv->state != TUSB320_ATTACHED_STATE_NONE) in tusb320_set_mode()
125 return -EBUSY; in tusb320_set_mode()
128 ret = regmap_write_bits(priv->regmap, TUSB320_REGA, in tusb320_set_mode()
132 dev_err(priv->dev, "failed to write mode: %d\n", ret); in tusb320_set_mode()
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/openbmc/linux/drivers/input/touchscreen/
H A Dpixcir_i2c_ts.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2011 Pixcir, Inc.
34 * using the RESET pin.
65 * struct pixcir_i2c_chip_data - chip related data
102 const struct pixcir_i2c_chip_data *chip = tsdata->chip; in pixcir_ts_parse()
106 i = chip->has_hw_ids ? 1 : 0; in pixcir_ts_parse()
107 readsize = 2 + tsdata->chip->max_fingers * (4 + i); in pixcir_ts_parse()
111 ret = i2c_master_send(tsdata->client, wrbuf, sizeof(wrbuf)); in pixcir_ts_parse()
113 dev_err(&tsdata->client->dev, in pixcir_ts_parse()
119 ret = i2c_master_recv(tsdata->client, rdbuf, readsize); in pixcir_ts_parse()
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/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-pinephone-pro.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 * https://files.pine64.org/doc/PinePhonePro/PinephonePro-Schematic-V1.0-20211127.pdf
12 /dts-v1/;
13 #include <dt-bindings/input/gpio-keys.h>
14 #include <dt-bindings/input/linux-event-codes.h>
16 #include "rk3399-opp.dtsi"
20 compatible = "pine64,pinephone-pro", "rockchip,rk3399";
21 chassis-type = "handset";
30 stdout-path = "serial2:115200n8";
33 adc-keys {
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/openbmc/linux/sound/soc/ti/
H A Ddavinci-i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * based on davinci-mcasp.c DT support
31 #include "edma-pcm.h"
32 #include "davinci-i2s.h"
34 #define DRV_NAME "davinci-i2s"
39 * - This driver supports the "Audio Serial Port" (ASP),
42 * - But it labels it a "Multi-channel Buffered Serial Port"
44 * backward-compatible, possibly explaining that confusion.
46 * - OMAP chips have a controller called McBSP, which is
49 * - Newer DaVinci chips have a controller called McASP,
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/openbmc/openbmc/meta-quanta/meta-gbs/recipes-gbs/gbs-sysinit/files/
H A Dgbs-sysinit.sh9 # http://www.apache.org/licenses/LICENSE-2.0
17 # shellcheck source=meta-quanta/meta-gbs/recipes-gbs/gbs-sysinit/files/gbs-gpio-common.sh
18 source /usr/libexec/gbs-gpio-common.sh
34 # Clear bit 16-23 to perserve all GPIO states across warm resets
40 # Clear bit 16-23 of CORSTC
84 # 0x00 - EVT
85 # 0x01 - DVT
86 # 0x10 - PVT
87 # 0x11 - MP
109 # GPIO76 UART_EN polarity inverted between DVT/PVT
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/openbmc/linux/drivers/watchdog/
H A Dsmsc37b787_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * any of this software. This material is provided "AS-IS" in
12 * (C) Copyright 2003-2006 Sven Anders <anders@anduras.de>
15 * 2003 - Created version 1.0 for Linux 2.4.x.
16 * 2006 - Ported to Linux 2.6, added nowayout and MAGICCLOSE
29 * that everything is in order, and that the watchdog should wait
38 * For an example userspace keep-alive daemon, see:
86 /* -- Low level function ----------------------------------------*/
124 /* -- Medium level functions ------------------------------------*/
128 /* -- General Purpose I/O Bit 1.2 -- in gpio_bit12()
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/openbmc/linux/drivers/spi/
H A Dspi-rspi.c1 // SPDX-License-Identifier: GPL-2.0
8 * Based on spi-sh.c:
21 #include <linux/dma-mapping.h>
31 #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */
32 #define RSPI_SPPCR 0x02 /* Pin Control Register */
41 #define RSPI_SPND 0x0e /* Next-Access Delay Register */
69 /* SPCR - Control Register */
78 #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
79 /* QSPI on R-Car Gen2 only */
80 #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */
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