| /openbmc/linux/arch/powerpc/include/asm/ |
| H A D | cpm2.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 * All CPM control and status is available through the CPM2 internal
27 /* Device sub-block and page codes.
72 /* CPM2-specific opcodes (see cpm.h for common opcodes)
113 * oversampled clock.
157 * get some microcode patches :-).
158 * The parameter ram space for the SMCs is fifty-some bytes, and
165 /* Define enough so I can at least use the serial port as a UART.
173 uint smc_rstate; /* Internal */
174 uint smc_idp; /* Internal */
[all …]
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| H A D | cpm1.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
8 * through the MPC8xx internal memory map. See immap.h for details.
11 * are needed. -- Dan
13 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
16 * or other use.
75 /* Define enough so I can at least use the serial port as a UART.
84 uint smc_rstate; /* Internal */
85 uint smc_idp; /* Internal */
86 ushort smc_rbptr; /* Internal */
87 ushort smc_ibc; /* Internal */
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/net/ |
| H A D | motorcomm,yt8xxx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
[all …]
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| H A D | amlogic,meson-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
20 - amlogic,meson6-dwmac
21 - amlogic,meson8b-dwmac
22 - amlogic,meson8m2-dwmac
23 - amlogic,meson-gxbb-dwmac
[all …]
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| H A D | ti,dp83867.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
34 nvmem-cells:
40 nvmem-cell-names:
42 - const: io_impedance_ctrl
[all …]
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| /openbmc/linux/Documentation/sound/cards/ |
| H A D | hdspm.rst | 2 Software Interface ALSA-DSP MADI Driver
5 (translated from German, so no good English ;-),
7 2004 - winfried ritsch
11 the Controls and startup-options are ALSA-Standard and only the
19 ------------------
21 * number of channels -- depends on transmission mode
24 use for a lower number of channels is only resource allocation,
29 * Single Speed -- 1..64 channels
37 * Double Speed -- 1..32 channels
40 Note: Choosing the 56-channel mode for
[all …]
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| /openbmc/u-boot/arch/powerpc/include/asm/ |
| H A D | cpm_85xx.h | 11 * All CPM control and status is available through the MPC8260 internal
28 /* Device sub-block and page codes.
73 * any CPM use, so we put the BDs there. The first 128 bytes are
82 #define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
85 #define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE)
131 #define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
132 #define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
260 uint scc_rstate; /* Internal */
261 uint scc_idp; /* Internal */
262 ushort scc_rbptr; /* Internal */
[all …]
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| /openbmc/linux/arch/arm/mach-omap2/ |
| H A D | omap_hwmod.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2009-2011 Nokia Corporation
6 * Copyright (C) 2011-2012 Texas Instruments, Inc.
13 * These headers and macros are used to define OMAP on-chip module
16 * omap_hwmod code, in arch/arm/mach-omap2/omap_hwmod.c (as of this
20 * - add interconnect error log structures
21 * - init_conn_id_bit (CONNID_BIT_VECTOR)
22 * - implement default hwmod SMS/SDRC flags?
23 * - move Linux-specific data ("non-ROM data") out
155 * struct omap_hwmod_rst_info - IPs reset lines use by hwmod
[all …]
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| H A D | msdi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
32 /* MSDI_TARGET_RESET_CLKD: clock divisor to use throughout the reset */
36 * omap_msdi_reset - reset the MSDI IP block
41 * successfully. This is not documented in the TRM. For CLKD, we use
42 * the value that results in the lowest possible clock rate, to attempt
53 /* Enable the MSDI core and internal clock */ in omap_msdi_reset()
59 omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs) in omap_msdi_reset()
65 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT); in omap_msdi_reset()
68 oh->name, c); in omap_msdi_reset()
70 /* Disable the MSDI internal clock */ in omap_msdi_reset()
|
| /openbmc/linux/Documentation/devicetree/bindings/iio/adc/ |
| H A D | ingenic,adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright 2019-2020 Artur Rojek
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Artur Rojek <contact@artur-rojek.eu>
17 ADC clients must use the format described in
18 https://github.com/devicetree-org/dt-schema/blob/master/schemas/iio/iio-consumer.yaml,
19 giving a phandle and IIO specifier pair ("io-channels") to the ADC controller.
24 - ingenic,jz4725b-adc
25 - ingenic,jz4740-adc
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/sound/ |
| H A D | renesas,fsi.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas FIFO-buffered Serial Interface (FSI)
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
13 - $ref: dai-common.yaml#
22 - items:
23 - enum:
24 - renesas,fsi2-sh73a0 # SH-Mobile AG5
25 - renesas,fsi2-r8a7740 # R-Mobile A1
[all …]
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| /openbmc/linux/Documentation/driver-api/media/ |
| H A D | camera-sensor.rst | 1 .. SPDX-License-Identifier: GPL-2.0
6 CSI-2 and parallel (BT.601 and BT.656) busses
7 ---------------------------------------------
9 Please see :ref:`transmitter-receiver`.
12 ---------------
14 Camera sensors have an internal clock tree including a PLL and a number of
15 divisors. The clock tree is generally configured by the driver based on a few
16 input parameters that are specific to the hardware:: the external clock frequency
20 The reason why the clock frequencies are so important is that the clock signals
23 elsewhere. Therefore only the pre-determined frequencies are configurable by the
[all …]
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| /openbmc/linux/Documentation/core-api/ |
| H A D | kernel-api.rst | 9 .. kernel-doc:: include/linux/list.h
10 :internal:
15 When writing drivers, you cannot in general use routines which are from
22 ------------------
24 .. kernel-doc:: lib/vsprintf.c
27 .. kernel-doc:: include/linux/kstrtox.h
30 .. kernel-doc:: lib/kstrtox.c
33 .. kernel-doc:: lib/string_helpers.c
37 -------------------
39 .. kernel-doc:: include/linux/fortify-string.h
[all …]
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| /openbmc/linux/include/linux/platform_data/ |
| H A D | ad7793.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
11 * enum ad7793_clock_source - AD7793 clock source selection
12 * @AD7793_CLK_SRC_INT: Internal 64 kHz clock, not available at the CLK pin.
13 * @AD7793_CLK_SRC_INT_CO: Internal 64 kHz clock, available at the CLK pin.
14 * @AD7793_CLK_SRC_EXT: Use external clock.
15 * @AD7793_CLK_SRC_EXT_DIV2: Use external clock divided by 2.
25 * enum ad7793_bias_voltage - AD7793 bias voltage selection
27 * @AD7793_BIAS_VOLTAGE_AIN1: Bias voltage connected to AIN1(-).
28 * @AD7793_BIAS_VOLTAGE_AIN2: Bias voltage connected to AIN2(-).
29 * @AD7793_BIAS_VOLTAGE_AIN3: Bias voltage connected to AIN3(-).
[all …]
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| /openbmc/linux/arch/riscv/boot/dts/starfive/ |
| H A D | jh7110-starfive-visionfive-2-v1.3b.dts | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7110-starfive-visionfive-2.dtsi"
12 compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
16 starfive,tx-use-rgmii-clk;
17 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
18 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
22 starfive,tx-use-rgmii-clk;
23 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
24 assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/phy/ |
| H A D | nvidia,tegra186-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
|
| H A D | phy-rockchip-naneng-combphy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3568-naneng-combphy
16 - rockchip,rk3588-naneng-combphy
23 - description: reference clock
24 - description: apb clock
25 - description: pipe clock
[all …]
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| H A D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
|
| H A D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
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| /openbmc/linux/drivers/clk/sunxi/ |
| H A D | clk-a20-gmac.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2013 Chen-Yu Tsai
7 * Chen-Yu Tsai <wens@csie.org>
10 #include <linux/clk-provider.h>
19 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
21 * This clock looks something like this
23 * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
24 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
25 * Ext. 125MHz RGMII TX clk >--|__divider__/ |
28 * The external 125 MHz reference is optional, i.e. GMAC can use its
[all …]
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| /openbmc/linux/include/linux/ |
| H A D | timekeeper_internal.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 * handling code or timekeeping internal code!
15 * struct tk_read_base - base structure for timekeeping readout
16 * @clock: Current clocksource used for timekeeping.
18 * @cycle_last: @clock cycle value at last update
23 * @base_real: Nanoseconds base value for clock REALTIME readout
31 * @base_real is for the fast NMI safe accessor to allow reading clock
35 struct clocksource *clock; member
46 * struct timekeeper - Structure holding internal timekeeping values.
52 * @offs_real: Offset clock monotonic -> clock realtime
[all …]
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| /openbmc/linux/include/linux/iio/common/ |
| H A D | inv_sensors_timestamp.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * struct inv_sensors_timestamp_chip - chip internal properties
11 * @clock_period: internal clock period in ns
12 * @jitter: acceptable jitter in per-mille
22 * struct inv_sensors_timestamp_interval - timestamps interval
32 * struct inv_sensors_timestamp_acc - accumulator for computing an estimation
35 * @values: table of all measured values, use for computing the mean
44 * struct inv_sensors_timestamp - timestamp management states
45 * @chip: chip internal characteristics
46 * @min_period: minimal acceptable clock period
[all …]
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| /openbmc/qemu/docs/devel/ |
| H A D | replay.rst | 13 execution. Execution recording writes a non-deterministic events log, which
16 non-deterministic events including external input, hardware clocks,
21 Devices' models that have non-deterministic input from external devices were
26 All non-deterministic events are coming from these devices. But to
33 …th Multi-target QEMU Simulator for Dynamic Analysis and Reverse Debugging <https://www.computer.or…
38 * wrappers for clock and time functions to save their return values in the log
43 * adding internal checkpoints for cpu and io synchronization
50 --------------------
52 QEMU should work in icount mode to use record/replay feature. icount was
54 of the virtual machine. We also use icount to control the occurrence of the
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/rtc/ |
| H A D | isil,isl1208.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <biju.das.jz@bp.renesas.com>
11 - Trent Piepho <tpiepho@gmail.com>
20 - isil,isl1208
21 - isil,isl1209
22 - isil,isl1218
23 - isil,isl1219
31 clock-names:
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | hi6220-clock.txt | 1 * Hisilicon Hi6220 Clock Controller
3 Clock control registers reside in different Hi6220 system controllers,
11 - compatible: the compatible should be one of the following strings to
12 indicate the clock controller functionality.
14 - "hisilicon,hi6220-acpu-sctrl"
15 - "hisilicon,hi6220-aoctrl"
16 - "hisilicon,hi6220-sysctrl"
17 - "hisilicon,hi6220-mediactrl"
18 - "hisilicon,hi6220-pmctrl"
19 - "hisilicon,hi6220-stub-clk"
[all …]
|