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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmaxlinear,gpy2xx.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Michael Walle <michael@walle.cc>
14 - $ref: ethernet-phy.yaml#
17 maxlinear,use-broken-interrupts:
19 Interrupts are broken on some GPY2xx PHYs in that they keep the
23 interrupts are disabled for this PHY and polling mode is used. If one
31 maxlinear,use-broken-interrupts: [ interrupts ]
[all …]
/openbmc/linux/arch/sh/
H A DKconfig.debug1 # SPDX-License-Identifier: GPL-2.0
4 bool "Use LinuxSH standard BIOS"
6 Say Y here if your target has the gdb-sh-stub
8 in FLASH or EPROM. The kernel will use standard BIOS calls during
11 on-board Ethernet interface, and shut down the hardware). Note this
30 used by the SH-IPL bootloader, starting very early in the boot
37 bool "Use 4Kb for kernel stacks instead of 8Kb"
38 depends on DEBUG_KERNEL && (MMU || BROKEN) && !PAGE_SIZE_64KB
40 If you say Y here the kernel will use a 4Kb stacksize for the
44 will also use IRQ stacks to compensate for the reduced stackspace.
[all …]
/openbmc/linux/arch/parisc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
79 select HAVE_DYNAMIC_FTRACE if $(cc-option,-fpatchable-function-entry=1,1)
90 The PA-RISC microprocessor is designed by Hewlett-Packard and used
92 and later HP3000 series). The PA-RISC Linux project home page is
152 # unless you want to implement ACPI on PA-RISC ... ;-)
168 depends on BROKEN
187 that can run on all 32-bit PA CPUs (albeit not optimally fast),
190 Specifying "PA8000" here will allow you to select a 64-bit kernel
196 Select this option for the PCX-L processor, as used in the
198 D200, D210, D300, D310 and E-class
[all …]
/openbmc/linux/Documentation/devicetree/bindings/serial/
H A D8250.yaml3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - devicetree@vger.kernel.org
13 - $ref: serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15 - if:
17 - required:
18 - aspeed,lpc-io-reg
19 - required:
20 - aspeed,lpc-interrupts
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/openbmc/qemu/hw/pci-host/
H A Dversatile.c4 * Copyright (c) 2006-2009 CodeSourcery.
18 #include "hw/qdev-properties.h"
25 * kernel also had the corresponding bug in setting up interrupts
27 * We automatically detect these broken kernels and flip back
28 * to the broken irq mapping by spotting guest writes to the
30 * interrupts are going to be routed. So we start in state
31 * ASSUME_OK on reset, and transition to either BROKEN or
33 * a slot where broken and correct interrupt mapping would differ.
34 * Once in either BROKEN or FORCE_OK we never transition again;
35 * this allows a newer kernel to use the INTERRUPT_LINE
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3xxx.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
33 compatible = "simple-bus";
34 #address-cells = <1>;
35 #size-cells = <1>;
38 dmac1_s: dma-controller@20018000 {
41 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
43 #dma-cells = <1>;
[all …]
H A Drk3036.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
13 interrupt-parent = <&gic>;
32 arm-pmu {
33 compatible = "arm,cortex-a7-pmu";
34 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dat91-vinco.dts6 * 2015 Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
28 * restriction, including without limitation the rights to use,
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 /dts-v1/;
54 stdout-path = "serial0:115200n8";
63 clock-frequency = <32768>;
67 clock-frequency = <12000000>;
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0
[all …]
/openbmc/linux/drivers/watchdog/
H A Dcpwd.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* cpwd.c - driver implementation for hardware watchdog
6 * interface and Solaris-compatible ioctls as best it is
11 * timer interrupts. We use a timer to periodically
43 #define WD_BADMODEL "SUNW,501-5336"
82 bool broken; member
97 /* Sun uses Altera PLD EPF8820ATC144-4
100 * 1) RIC - sends an interrupt when triggered
101 * 2) XIR - asserts XIR_B_RESET when triggered, resets CPU
102 * 3) POR - asserts POR_B_RESET when triggered, resets CPU, backplane, board
[all …]
/openbmc/linux/arch/alpha/kernel/
H A Dpci_impl.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 * We can't just blindly use 64K for machines with EISA busses; they
15 * may also have PCI-PCI bridges present, and then we'd configure the
20 * BIOSes (Millennium for one) use PCI Config space "mechanism #2"
31 * a single bit set. This is so that devices like the broken Myrinet card
38 * that get passed through the PCI<->ISA bridge chip. Although this causes
39 * us to set the PCI->Mem window bases lower than normal, we still allocate
44 * We accept the risk that a broken Myrinet card will be put into a true XL
47 #define XL_DEFAULT_MEM_BASE ((16+2)*1024*1024) /* 16M to 64M-1 is avail */
58 * memory addresses. However, we do not use them all, in order to
[all …]
/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Dmarvell,mv64xxx-i2c.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/marvell,mv64xxx-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gregory CLEMENT <gregory.clement@bootlin.com>
15 - const: allwinner,sun4i-a10-i2c
16 - items:
17 - const: allwinner,sun7i-a20-i2c
18 - const: allwinner,sun4i-a10-i2c
19 - const: allwinner,sun6i-a31-i2c
[all …]
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Darm,arch_timer_mmio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
17 The memory mapped timer is attached to a GIC to deliver its interrupts via SPIs.
22 - enum:
23 - arm,armv7-timer-mem
29 '#address-cells':
32 '#size-cells':
[all …]
H A Darm,arch_timer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
19 to deliver its interrupts via SPIs.
24 - items:
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dmpic.h1 /* SPDX-License-Identifier: GPL-2.0 */
27 * 0b00 = pass through (interrupts routed to IRQ0)
71 * Per-Processor registers
92 * Per-source registers
149 * Per-Processor registers
162 * Per-source registers
287 /* vector numbers used for FSL MPIC error interrupts */
355 /* Set this for a big-endian MPIC */
357 /* Broken U3 MPIC */
359 /* Broken IPI registers (autodetected) */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
H A Ducc.txt4 - device_type : should be "network", "hldc", "uart", "transparent"
6 - compatible : could be "ucc_geth" or "fsl_atm" and so on.
7 - cell-index : the ucc number(1-8), corresponding to UCCx in UM.
8 - reg : Offset and length of the register set for the device
9 - interrupts : <a b> where a is the interrupt number and b is a
14 - pio-handle : The phandle for the Parallel I/O port configuration.
15 - port-number : for UART drivers, the port number to use, between 0 and 3.
18 CPM UART driver, the port-number is required for the QE UART driver.
19 - soft-uart : for UART drivers, if specified this means the QE UART device
20 driver should use "Soft-UART" mode, which is needed on some SOCs that have
[all …]
/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsun5i-a13-licheepi-one.dts4 * Based on sun5i-a13-olinuxino.dts, which is
5 * Copyright 2012 Maxime Ripard <maxime.ripard@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
28 * restriction, including without limitation the rights to use,
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 /dts-v1/;
48 #include "sun5i-a13.dtsi"
49 #include "sunxi-common-regulators.dtsi"
51 #include <dt-bindings/gpio/gpio.h>
52 #include <dt-bindings/input/input.h>
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32746g-eval.dts2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
24 * restriction, including without limitation the rights to use,
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 /dts-v1/;
45 #include "stm32f746-pinctrl.dtsi"
46 #include <dt-bindings/input/input.h>
47 #include <dt-bindings/interrupt-controller/irq.h>
50 model = "STMicroelectronics STM32746g-EVAL board";
51 compatible = "st,stm32746g-eval", "st,stm32f746";
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Duncore-cache.json8 … specified by the subevent. Does not include addressless requests such as locks and interrupts.",
18 … specified by the subevent. Does not include addressless requests such as locks and interrupts.",
23 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.…
28 … specified by the subevent. Does not include addressless requests such as locks and interrupts.",
38 … specified by the subevent. Does not include addressless requests such as locks and interrupts.",
49 … specified by the subevent. Does not include addressless requests such as locks and interrupts.",
158 …Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, p…
167 …Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, p…
176 …Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, p…
185 …Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, p…
[all …]
/openbmc/linux/arch/m68k/
H A DKconfig.devices1 # SPDX-License-Identifier: GPL-2.0
6 depends on BROKEN && (Q40 || SUN3X)
12 bool "Use power LED as a heartbeat" if AMIGA || APOLLO || ATARI || Q40
15 Use the power-on LED on your machine as a load meter. The exact
16 behavior is platform-dependent, but normally the flash frequency is
17 a hyperbolic function of the 5-minute load average.
19 # We have a dedicated heartbeat LED. :-)
75 ROM port. The driver works by polling instead of interrupts, so it
92 If you want to be able to use the DSP56001 in Falcons, say Y. This
102 If you want to use your Amiga's built-in serial port in Linux,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <maz@kernel.org>
14 Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
16 Interrupts (LPI).
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
[all …]
/openbmc/linux/include/linux/platform_data/
H A Dbrcmfmac.h4 * Permission to use, copy, modify, and/or distribute this software for any
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
34 * Note: the brcmfmac can be loaded as module or be statically built-in into
35 * the kernel. If built-in then do note that it uses module_init (and
38 * it built-in to the kernel then use a higher initcall then device_initcall
48 * enum brcmf_bus_type - Bus type identifier. Currently SDIO, USB and PCIE are
59 * struct brcmfmac_sdio_pd - SDIO Device specific platform data.
61 * @txglomsz: SDIO txglom size. Use 0 if default of driver is to be
68 * @oob_irq_supported: does the board have support for OOB interrupts. SDIO
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/pci/
H A Dbase.c7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
33 struct nvkm_pci *pci = device->pci; in nvkm_pci_msi_rearm()
35 if (pci && pci->msi) in nvkm_pci_msi_rearm()
36 pci->func->msi_rearm(pci); in nvkm_pci_msi_rearm()
42 return pci->func->rd32(pci, addr); in nvkm_pci_rd32()
48 pci->func->wr08(pci, addr, data); in nvkm_pci_wr08()
54 pci->func->wr32(pci, addr, data); in nvkm_pci_wr32()
60 u32 data = pci->func->rd32(pci, addr); in nvkm_pci_mask()
61 pci->func->wr32(pci, addr, (data & ~mask) | value); in nvkm_pci_mask()
[all …]
/openbmc/linux/Documentation/accel/qaic/
H A Dqaic.rst1 .. SPDX-License-Identifier: GPL-2.0-only
10 Interrupts chapter
18 non-empty and generate MSIs at a rate equivalent to the speed of the
34 generates 100k IRQs per second (per /proc/interrupts) is reduced to roughly 64
49 QAIC handles and enforces the required little endianness and 64-bit alignment,
53 The terminate transaction is of particular use to QAIC. QAIC is not aware of
98 call is non-blocking. Success only indicates that the BOs have been queued
113 processed and can be re-queued to the device, or a timeout occurs.
135 may only use memory they allocate, and DBCs that are assigned to their
146 Configures QAIC to use a polling thread for datapath events instead of relying
[all …]
/openbmc/linux/Documentation/admin-guide/blockdev/
H A Dfloppy.rst19 Example: If your kernel is called linux-2.6.9, type the following line
22 linux-2.6.9 floppy=thinkpad
25 of linux-2.6.9::
31 linux-2.6.9 floppy=daring floppy=two_fdc
43 If you use the floppy driver as a module, use the following syntax::
81 0x370, and if you use the 'cmos' option.
84 Tells the floppy driver that you have a Thinkpad. Thinkpads use an
91 Tells the floppy driver not to use Dma for data transfers.
96 and is thus harder to find, whereas non-dma buffers may be
99 later are OK. You also need at least a 486 to use nodma.
[all …]
/openbmc/linux/Documentation/virt/hyperv/
H A Dvmbus.rst1 .. SPDX-License-Identifier: GPL-2.0
5 VMbus is a software construct provided by Hyper-V to guest VMs. It
7 devices that Hyper-V presents to guest VMs. The control path is
11 and the synthetic device implementation that is part of Hyper-V, and
12 signaling primitives to allow Hyper-V and the guest to interrupt
17 establishes the VMbus control path with the Hyper-V host, then
21 Most synthetic devices offered by Hyper-V have a corresponding Linux
29 * PCI device pass-thru
34 * Key/Value Pair (KVP) exchange with Hyper-V
35 * Hyper-V online backup (a.k.a. VSS)
[all …]

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