| /openbmc/linux/Documentation/devicetree/bindings/phy/ |
| H A D | qcom,msm8996-qmp-usb3-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (USB, MSM8996)
10 - Vinod Koul <vkoul@kernel.org>
13 QMP PHY controller supports physical layer functionality for a number of
17 qcom,sc8280xp-qmp-usb3-uni-phy.yaml.
22 - qcom,ipq6018-qmp-usb3-phy
23 - qcom,ipq8074-qmp-usb3-phy
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| H A D | renesas,usb3-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car generation 3 USB 3.0 PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,r8a774a1-usb3-phy # RZ/G2M
17 - renesas,r8a774b1-usb3-phy # RZ/G2N
18 - renesas,r8a774e1-usb3-phy # RZ/G2H
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| H A D | socionext,uniphier-usb3ss-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 Super-Speed (SS) PHY
10 This describes the devicetree bindings for PHY interfaces built into
11 USB3 controller implemented on Socionext UniPhier SoCs.
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about Super-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
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| H A D | qcom,sc8280xp-qmp-usb43dp-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP USB4-USB3-DP PHY controller (SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
13 The QMP PHY controller supports physical layer functionality for a number of
19 - qcom,sc7180-qmp-usb3-dp-phy
20 - qcom,sc7280-qmp-usb3-dp-phy
21 - qcom,sc8180x-qmp-usb3-dp-phy
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| H A D | qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (USB, SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
13 The QMP PHY controller supports physical layer functionality for a number of
19 - qcom,ipq9574-qmp-usb3-phy
20 - qcom,qcm2290-qmp-usb3-phy
21 - qcom,sa8775p-qmp-usb3-uni-phy
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| H A D | socionext,uniphier-usb3hs-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 High-Speed (HS) PHY
10 This describes the devicetree bindings for PHY interfaces built into
11 USB3 controller implemented on Socionext UniPhier SoCs.
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about High-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
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| H A D | bcm-ns-usb3-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/bcm-ns-usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Northstar USB 3.0 PHY
10 Initialization of USB 3.0 PHY depends on Northstar version. There are currently
18 - Rafał Miłecki <rafal@milecki.pl>
23 - brcm,ns-ax-usb3-phy
24 - brcm,ns-bx-usb3-phy
30 usb3-dmp-syscon:
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| H A D | nvidia,tegra194-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
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| H A D | amlogic,g12a-usb3-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/amlogic,g12a-usb3-pcie-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic G12A USB3 + PCIE Combo PHY
11 - Neil Armstrong <neil.armstrong@linaro.org>
16 - amlogic,g12a-usb3-pcie-phy
24 clock-names:
26 - const: ref_clk
31 reset-names:
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| H A D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
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| H A D | allwinner,sun50i-h6-usb3-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/allwinner,sun50i-h6-usb3-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Allwinner H6 USB3 PHY
11 - Ondrej Jirman <megous@megous.com>
16 - allwinner,sun50i-h6-usb3-phy
27 "#phy-cells":
31 - compatible
32 - reg
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| H A D | phy-rockchip-typec.txt | 1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
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| H A D | nvidia,tegra186-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
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| H A D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
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| H A D | ti-phy.txt | 1 TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
3 OMAP CONTROL PHY
6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
11 e.g. USB3 PHY and SATA PHY on OMAP5.
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
14 e.g. PCIE PHY in DRA7x
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
[all …]
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| /openbmc/linux/drivers/phy/broadcom/ |
| H A D | phy-bcm-ns-usb3.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom Northstar USB 3.0 PHY Driver
22 #include <linux/phy/phy.h>
53 struct phy *phy; member
58 .compatible = "brcm,ns-ax-usb3-phy",
62 .compatible = "brcm,ns-bx-usb3-phy",
68 static int bcm_ns_usb3_mdio_phy_write(struct bcm_ns_usb3 *usb3, u16 reg,
71 static int bcm_ns_usb3_phy_init_ns_bx(struct bcm_ns_usb3 *usb3) in bcm_ns_usb3_phy_init_ns_bx() argument
75 /* USB3 PLL Block */ in bcm_ns_usb3_phy_init_ns_bx()
76 err = bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG, in bcm_ns_usb3_phy_init_ns_bx()
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/soc/socionext/ |
| H A D | socionext,uniphier-dwc3-glue.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-dwc3-glue.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier SoC DWC3 USB3.0 glue layer
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 DWC3 USB3.0 glue layer implemented on Socionext UniPhier SoCs is
15 USB3.0 component.
20 - enum:
21 - socionext,uniphier-pro4-dwc3-glue
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| /openbmc/linux/drivers/phy/tegra/ |
| H A D | xusb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
12 #include <linux/phy/phy.h>
13 #include <linux/phy/tegra/xusb.h>
24 static struct phy *tegra_xusb_pad_of_xlate(struct device *dev, in tegra_xusb_pad_of_xlate()
28 struct phy *phy = NULL; in tegra_xusb_pad_of_xlate() local
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
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| H A D | xusb-tegra186.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
10 #include <linux/phy/phy.h>
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
280 writel(value, priv->ao_regs + offset); in ao_writel()
285 return readl(priv->ao_regs + offset); in ao_readl()
294 /* USB 2.0 UTMI PHY support */
304 return ERR_PTR(-ENOMEM); in tegra186_usb2_lane_probe()
306 INIT_LIST_HEAD(&usb2->base.list); in tegra186_usb2_lane_probe()
307 usb2->base.soc = &pad->soc->lanes[index]; in tegra186_usb2_lane_probe()
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| /openbmc/linux/drivers/phy/socionext/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # PHY drivers for Socionext platforms.
7 tristate "UniPhier USB2 PHY driver"
13 Enable this to support USB PHY implemented on USB2 controller
15 with USB 2.0 PHY that is part of the UniPhier SoC.
16 In case of Pro4, it is necessary to specify this USB2 PHY instead
17 of USB3 HS-PHY.
20 tristate "UniPhier USB3 PHY driver"
25 Enable this to support USB PHY implemented in USB3 controller
26 on UniPhier SoCs. This controller supports USB3.0 and lower speed.
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| H A D | phy-uniphier-usb3ss.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * phy-uniphier-usb3ss.c - SS-PHY driver for Socionext UniPhier USB3 controller
4 * Copyright 2015-2018 Socionext Inc.
19 #include <linux/phy/phy.h>
73 writel(data, priv->base + SSPHY_TESTI); in uniphier_u3ssphy_testio_write()
74 readl(priv->base + SSPHY_TESTO); in uniphier_u3ssphy_testio_write()
75 readl(priv->base + SSPHY_TESTO); in uniphier_u3ssphy_testio_write()
82 u8 field_mask = GENMASK(p->field.msb, p->field.lsb); in uniphier_u3ssphy_set_param()
87 val |= FIELD_PREP(TESTI_ADR_MASK, p->field.reg_no); in uniphier_u3ssphy_set_param()
89 val = readl(priv->base + SSPHY_TESTO) & TESTO_DAT_MASK; in uniphier_u3ssphy_set_param()
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| /openbmc/linux/arch/arm64/boot/dts/nvidia/ |
| H A D | tegra234-p3768-0000.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 compatible = "nvidia,p3768-0000";
11 stdout-path = "serial0:115200n8";
23 vcc-supply = <&vdd_1v8_sys>;
24 address-width = <8>;
27 read-only;
36 assigned-clocks = <&bpmp TEGRA234_CLK_PWM3>;
37 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
47 usb2-0 {
52 usb2-1 {
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| H A D | tegra234-p3737-0000+p3701-0000.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
7 #include "tegra234-p3701-0000.dtsi"
8 #include "tegra234-p3737-0000.dtsi"
12 compatible = "nvidia,p3737-0000+p3701-0000", "nvidia,p3701-0000", "nvidia,tegra234";
22 stdout-path = "serial0:115200n8";
27 compatible = "nvidia,tegra194-hsuart";
28 reset-names = "serial";
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/usb/ |
| H A D | mediatek,mtk-xhci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek USB3 xHCI
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-xhci.yaml
19 case 2: supports dual-role mode, and the host is based on xHCI driver.
25 - enum:
26 - mediatek,mt2701-xhci
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| H A D | amlogic,meson-g12a-usb-ctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY.
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
22 The DWC3 Glue controls the PHY routing and power, an interrupt line is
[all …]
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