/openbmc/linux/Documentation/devicetree/bindings/usb/ |
H A D | nvidia,tegra124-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/nvidia,tegra124-xusb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 20 - description: NVIDIA Tegra124 21 const: nvidia,tegra124-xusb 23 - description: NVIDIA Tegra132 25 - const: nvidia,tegra132-xusb [all …]
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H A D | nvidia,tegra210-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/nvidia,tegra210-xusb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 18 const: nvidia,tegra210-xusb 22 - description: base and length of the xHCI host registers 23 - description: base and length of the XUSB FPCI registers 24 - description: base and length of the XUSB IPFS registers [all …]
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H A D | twlxxxx-usb.txt | 1 USB COMPARATOR OF TWL CHIPS 3 TWL6030 USB COMPARATOR 4 - compatible : Should be "ti,twl6030-usb" 5 - interrupts : Two interrupt numbers to the cpu should be specified. First 8 usb interrupt number that raises VBUS interrupts when the controller has to 10 - usb-supply : phandle to the regulator device tree node. It should be vusb 13 twl6030-usb { 14 compatible = "ti,twl6030-usb"; 19 &twl6030-usb { 20 usb-supply = <&vusb>; [all …]
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H A D | nvidia,tegra194-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/nvidia,tegra194-xusb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 18 const: nvidia,tegra194-xusb 22 - description: base and length of the xHCI host registers 23 - description: base and length of the XUSB FPCI registers 25 reg-names: [all …]
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H A D | nvidia,tegra186-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/nvidia,tegra186-xusb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 18 const: nvidia,tegra186-xusb 22 - description: base and length of the xHCI host registers 23 - description: base and length of the XUSB FPCI registers 25 reg-names: [all …]
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H A D | msm-hsusb.txt | 6 - compatible: Should contain "qcom,ehci-host" 7 - regs: offset and length of the register set in the memory map 8 - usb-phy: phandle for the PHY device 13 compatible = "qcom,ehci-host"; 15 usb-phy = <&usb_otg>; 18 USB PHY with optional OTG: 21 - compatible: Should contain: 22 "qcom,usb-otg-ci" for chipsets with ChipIdea 45nm PHY 23 "qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY 25 - regs: Offset and length of the register set in the memory map [all …]
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H A D | nvidia,tegra-xudc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/nvidia,tegra-xudc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 The Tegra XUDC controller supports both USB 2.0 HighSpeed/FullSpeed and 11 USB 3.0 SuperSpeed protocols. 14 - Nagarjuna Kristam <nkristam@nvidia.com> 15 - JC Kuo <jckuo@nvidia.com> 16 - Thierry Reding <treding@nvidia.com> 21 - enum: [all …]
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H A D | microchip,usb5744.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/microchip,usb5744.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Microchip USB5744 4-port Hub Controller 10 Microchip's USB5744 SmartHubTM IC is a 4 port, SuperSpeed (SS)/Hi-Speed (HS), 11 low power, low pin count configurable and fully compliant with the USB 3.1 13 (LS) USB signaling, offering complete coverage of all defined USB operating 14 speeds. The new SuperSpeed hubs operate in parallel with the USB 2.0 16 USB 2.0 traffic. [all …]
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/openbmc/linux/Documentation/devicetree/bindings/power/supply/ |
H A D | x-powers,axp20x-usb-power-supply.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/power/supply/x-powers,axp20x-usb-power-supply.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: AXP20x USB power-supply 11 variations such as the former being able to set the VBUS power supply max 15 - Chen-Yu Tsai <wens@csie.org> 16 - Sebastian Reichel <sre@kernel.org> 19 - $ref: power-supply.yaml# 24 - enum: [all …]
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/openbmc/linux/Documentation/devicetree/bindings/phy/ |
H A D | nvidia,tegra186-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller 24 contains a software-configurable mux that sits between the I/O controller [all …]
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H A D | allwinner,sun8i-h3-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-h3-usb-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Allwinner H3 USB PHY 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 14 "#phy-cells": 19 - allwinner,sun8i-h3-usb-phy 20 - allwinner,sun50i-h616-usb-phy [all …]
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H A D | allwinner,sun6i-a31-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-usb-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Allwinner A31 USB PHY 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 14 "#phy-cells": 18 const: allwinner,sun6i-a31-usb-phy 22 - description: PHY Control registers [all …]
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H A D | allwinner,sun8i-a83t-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-a83t-usb-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Allwinner A83t USB PHY 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 14 "#phy-cells": 18 const: allwinner,sun8i-a83t-usb-phy 22 - description: PHY Control registers [all …]
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H A D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller 24 contains a software-configurable mux that sits between the I/O controller [all …]
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H A D | nvidia,tegra194-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller 24 contains a software-configurable mux that sits between the I/O controller [all …]
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H A D | qcom,usb-snps-femto-v2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/qcom,usb-snps-femto-v2.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Qualcomm Synopsys Femto High-Speed USB PHY V2 10 - Wesley Cheng <quic_wcheng@quicinc.com> 13 Qualcomm High-Speed USB PHY 18 - items: 19 - enum: 20 - qcom,sa8775p-usb-hs-phy [all …]
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H A D | allwinner,sun4i-a10-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/phy/allwinner,sun4i-a10-usb-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Allwinner A10 USB PHY 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 14 "#phy-cells": 19 - allwinner,sun4i-a10-usb-phy 20 - allwinner,sun7i-a20-usb-phy [all …]
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H A D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller 24 contains a software-configurable mux that sits between the I/O controller [all …]
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H A D | allwinner,sun8i-r40-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-r40-usb-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Allwinner R40 USB PHY 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 14 "#phy-cells": 18 const: allwinner,sun8i-r40-usb-phy 22 - description: PHY Control registers [all …]
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H A D | allwinner,sun8i-a23-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-a23-usb-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Allwinner A23 USB PHY 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 14 "#phy-cells": 19 - allwinner,sun8i-a23-usb-phy 20 - allwinner,sun8i-a33-usb-phy [all …]
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H A D | allwinner,sun50i-a64-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Allwinner A64 USB PHY 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 14 "#phy-cells": 19 - allwinner,sun20i-d1-usb-phy 20 - allwinner,sun50i-a64-usb-phy [all …]
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H A D | allwinner,sun50i-h6-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/phy/allwinner,sun50i-h6-usb-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Allwinner H6 USB PHY 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 14 "#phy-cells": 18 const: allwinner,sun50i-h6-usb-phy 22 - description: PHY Control registers [all …]
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H A D | allwinner,sun5i-a13-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/phy/allwinner,sun5i-a13-usb-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Allwinner A13 USB PHY 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 14 "#phy-cells": 18 const: allwinner,sun5i-a13-usb-phy 22 - description: PHY Control registers [all …]
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H A D | qcom,usb-8x16-phy.txt | 1 Qualcomm's APQ8016/MSM8916 USB transceiver controller 3 - compatible: 6 Definition: Should contain "qcom,usb-8x16-phy". 8 - reg: 10 Value type: <prop-encoded-array> 11 Definition: USB PHY base address and length of the register map 13 - clocks: 15 Value type: <prop-encoded-array> 16 Definition: See clock-bindings.txt section "consumers". List of 20 - clock-names: [all …]
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/openbmc/u-boot/doc/device-tree-bindings/phy/ |
H A D | sun4i-usb-phy.txt | 1 Allwinner sun4i USB PHY 2 ----------------------- 5 - compatible : should be one of 6 * allwinner,sun4i-a10-usb-phy 7 * allwinner,sun5i-a13-usb-phy 8 * allwinner,sun6i-a31-usb-phy 9 * allwinner,sun7i-a20-usb-phy 10 * allwinner,sun8i-a23-usb-phy 11 * allwinner,sun8i-a33-usb-phy 12 * allwinner,sun8i-a83t-usb-phy [all …]
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