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/openbmc/linux/drivers/net/can/usb/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "CAN USB interfaces"
3 depends on USB
12 tristate "EMS CPC-USB/ARM7 CAN/USB interface"
14 This driver is for the one channel CPC-USB/ARM7 CAN/USB interface
15 from EMS Dr. Thomas Wuensche (http://www.ems-wuensche.de).
18 tristate "esd electronics gmbh CAN/USB interfaces"
20 This driver adds supports for several CAN/USB interfaces
24 - esd CAN-USB/2
25 - esd CAN-USB/Micro
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,usb-snps-femto-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-snps-femto-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Synopsys Femto High-Speed USB PHY V2
10 - Wesley Cheng <quic_wcheng@quicinc.com>
13 Qualcomm High-Speed USB PHY
18 - items:
19 - enum:
20 - qcom,sa8775p-usb-hs-phy
[all …]
H A Dqcom,usb-hs-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm's USB HS PHY
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
17 - qcom,usb-hs-phy-apq8064
18 - qcom,usb-hs-phy-msm8960
24 reset-names:
33 reset-names:
[all …]
H A Dbrcm,stingray-usb-phy.txt1 Broadcom Stingray USB PHY
4 - compatible : should be one of the listed compatibles
5 - "brcm,sr-usb-combo-phy" is combo PHY has two PHYs, one SS and one HS.
6 - "brcm,sr-usb-hs-phy" is a single HS PHY.
7 - reg: offset and length of the PHY blocks registers
8 - #phy-cells:
9 - Must be 1 for brcm,sr-usb-combo-phy as it expects one argument to indicate
10 the PHY number of two PHYs. 0 for HS PHY and 1 for SS PHY.
11 - Must be 0 for brcm,sr-usb-hs-phy.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties
[all …]
H A Dphy-stm32-usbphyc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 USB HS PHY controller
22 |_ PHY port#2 ----| |________________
27 - Amelie Delaunay <amelie.delaunay@foss.st.com>
31 const: st,stm32mp1-usbphyc
42 "#address-cells":
45 "#size-cells":
[all …]
H A Dtransmit-amplitude.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/transmit-amplitude.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Binding describing the peak-to-peak transmit amplitude for common PHYs
14 - Marek Behún <kabel@kernel.org>
17 tx-p2p-microvolt:
19 Transmit amplitude voltages in microvolts, peak-to-peak. If this property
21 'tx-p2p-microvolt-names' property must be provided and contain
24 tx-p2p-microvolt-names:
[all …]
H A Dqcom,ipq806x-usb-phy-hs.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-hs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm ipq806x usb DWC3 HS PHY CONTROLLER
10 - Ansuel Smith <ansuelsmth@gmail.com>
13 DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
19 const: qcom,ipq806x-usb-phy-hs
21 "#phy-cells":
31 clock-names:
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H A Dqcom-usb-ipq4019-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom-usb-ipq4019-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcom IPQ40xx Dakota HS/SS USB PHY
10 - Robert Marko <robert.marko@sartura.hr>
15 - qcom,usb-ss-ipq4019-phy
16 - qcom,usb-hs-ipq4019-phy
24 reset-names:
26 - const: por_rst
[all …]
H A Dqcom,usb-hs-28nm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-hs-28nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Synopsys DesignWare Core 28nm High-Speed PHY
10 - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
13 Qualcomm Low-Speed, Full-Speed, Hi-Speed 28nm USB PHY
18 - qcom,usb-hs-28nm-femtophy
23 "#phy-cells":
28 - description: rpmcc ref clock
[all …]
H A Dnvidia,tegra20-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra USB PHY
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
17 - items:
18 - enum:
[all …]
H A Drenesas,rcar-gen2-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,rcar-gen2-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Gen2 USB PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,usb-phy-r8a7742 # RZ/G1H
17 - renesas,usb-phy-r8a7743 # RZ/G1M
18 - renesas,usb-phy-r8a7744 # RZ/G1N
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/openbmc/linux/drivers/phy/st/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 tristate "ST SPEAR1310-MIPHY driver"
21 tristate "ST SPEAR1340-MIPHY driver"
37 tristate "STMicroelectronics STM32 USB HS PHY Controller driver"
42 Enable this to support the High-Speed USB transceivers that are part
45 This driver controls the entire USB PHY block: the USB PHY controller
46 (USBPHYC) and the two 8-bit wide UTMI+ interfaces. First interface is
47 used by an HS USB Host controller, and the second one is shared
48 between an HS USB OTG controller and an HS USB Host controller,
49 selected by a USB switch.
/openbmc/qemu/hw/usb/
H A Ddev-hid.c2 * QEMU USB HID devices
28 #include "hw/usb.h"
35 #include "hw/usb/hid.h"
36 #include "hw/qdev-properties.h"
48 #define TYPE_USB_HID "usb-hid"
67 [STR_PRODUCT_MOUSE] = "QEMU USB Mouse",
68 [STR_PRODUCT_TABLET] = "QEMU USB Tablet",
69 [STR_PRODUCT_KEYBOARD] = "QEMU USB Keyboard",
136 .bInterval = 7, /* 2 ^ (8-1) * 125 usecs = 8 ms */
196 .bInterval = 4, /* 2 ^ (4-1) * 125 usecs = 1 ms */
[all …]
/openbmc/linux/drivers/phy/qualcomm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 tristate "Atheros AR71XX/9XXX USB PHY driver"
12 Enable this to support the USB PHY on Atheros AR71XX/9XXX SoCs.
32 tristate "Qualcomm IPQ4019 USB PHY driver"
36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
98 tristate "Qualcomm QMP USB PHY Driver"
102 Enable this to support the QMP USB PHY transceiver that is used
106 tristate "Qualcomm QMP legacy USB PHY Driver"
110 Enable this legacy driver to support the QMP USB+DisplayPort Combo
123 Enable this to support the HighSpeed QUSB2 PHY transceiver for USB
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_ATH79_USB) += phy-ath79-usb.o
3 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
4 obj-$(CONFIG_PHY_QCOM_EDP) += phy-qcom-edp.o
5 obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
6 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
7 obj-$(CONFIG_PHY_QCOM_M31_USB) += phy-qcom-m31.o
8 obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o
10 obj-$(CONFIG_PHY_QCOM_QMP_COMBO) += phy-qcom-qmp-combo.o
11 obj-$(CONFIG_PHY_QCOM_QMP_PCIE) += phy-qcom-qmp-pcie.o
[all …]
H A Dphy-qcom-snps-femto-v2.c1 // SPDX-License-Identifier: GPL-2.0
82 "vdda-pll", "vdda33", "vdda18",
110 * struct qcom_snps_hsphy - snps hs phy attributes
115 * @base: iomapped memory space for snps hs phy
143 struct device *dev = hsphy->dev; in qcom_snps_hsphy_clk_init()
145 hsphy->num_clks = 2; in qcom_snps_hsphy_clk_init()
146 hsphy->clks = devm_kcalloc(dev, hsphy->num_clks, sizeof(*hsphy->clks), GFP_KERNEL); in qcom_snps_hsphy_clk_init()
147 if (!hsphy->clks) in qcom_snps_hsphy_clk_init()
148 return -ENOMEM; in qcom_snps_hsphy_clk_init()
154 hsphy->clks[0].id = "cfg_ahb"; in qcom_snps_hsphy_clk_init()
[all …]
/openbmc/u-boot/drivers/phy/
H A DKconfig13 PHYs are commonly used for high speed interfaces such as Serial-ATA
29 PHYs are commonly used for high speed interfaces such as Serial-ATA
48 Support for a no-op PHY driver (stubbed PHY driver).
57 Support for a no-op PHY driver (stubbed PHY driver) in the SPL.
114 tristate "Renesas R-Car Gen2 USB PHY"
117 Support for the Renesas R-Car Gen2 USB PHY. This driver operates the
122 tristate "Renesas R-Car Gen3 USB PHY"
126 Support for the Renesas R-Car Gen3 USB PHY. This driver operates the
127 PHY connected to EHCI USB module and controls USB OTG operation.
130 tristate "STMicroelectronics STM32 SoC USB HS PHY driver"
[all …]
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dmediatek,mtk-xhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-xhci.yaml
19 case 2: supports dual-role mode, and the host is based on xHCI driver.
25 - enum:
26 - mediatek,mt2701-xhci
27 - mediatek,mt2712-xhci
[all …]
H A Dmediatek,mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/mediatek,mtu3.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-drd.yaml
23 - enum:
24 - mediatek,mt2712-mtu3
25 - mediatek,mt8173-mtu3
26 - mediatek,mt8183-mtu3
[all …]
H A Dsnps,dwc3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/snps,dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 be presented as a standalone DT node with an optional vendor-specific
18 - $ref: usb-drd.yaml#
19 - if:
25 - dr_mode
27 $ref: usb.yaml#
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,rcar-usb2-clock-sel.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,rcar-usb2-clock-sel.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car USB 2.0 clock selector
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
19 Case 1: An external clock connects to R-Car SoC
20 +----------+ +--- R-Car ---------------------+
21 |External |---|USB_EXTAL ---> all usb channels|
23 +----------+ +-------------------------------+
[all …]
/openbmc/linux/Documentation/devicetree/bindings/connector/
H A Dusb-connector.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/connector/usb-connector.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: USB Connector
10 - Rob Herring <robh@kernel.org>
13 A USB connector node represents a physical USB connector. It should be a child
14 of a USB interface controller or a separate node when it is attached to both
15 MUX and USB interface controller.
20 - enum:
[all …]
/openbmc/linux/drivers/usb/cdns3/
H A Dcdns3-gadget.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2018-2019 Cadence.
6 * Copyright (C) 2017-2018 NXP
14 #include <linux/usb/gadget.h>
15 #include <linux/dma-direction.h>
18 * USBSS-DEV register interface.
23 * struct cdns3_usb_regs - device controller registers.
29 * @usb_ien: USB Interrupt Enable.
30 * @usb_ists: USB Interrupt Status.
53 * @buf_addr: Address for On-chip Buffer operations.
[all …]
/openbmc/linux/drivers/usb/host/
H A Dehci-xilinx-of.c1 // SPDX-License-Identifier: GPL-2.0+
3 * EHCI HCD (Host Controller Driver) for USB.
9 * Based on "ehci-ppc-of.c" by Valentine Barshak <vbarshak@ru.mvista.com>
10 * and "ehci-ppc-soc.c" by Stefan Roese <sr@denx.de>
11 * and "ohci-ppc-of.c" by Sylvain Munaut <tnt@246tNt.com>
23 * ehci_xilinx_port_handed_over - hand the port out if failed to enable it
27 * This function is used as a place to tell the user that the Xilinx USB host
28 * controller does support LS devices. And in an HS only configuration, it
34 * the USB bus. In those cases, the messages printed here are not helpful.
40 dev_warn(hcd->self.controller, "port %d cannot be enabled\n", portnum); in ehci_xilinx_port_handed_over()
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp135f-dk.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/regulator/st,stm32mp13-regulator.h>
15 #include "stm32mp13-pinctrl.dtsi"
18 model = "STMicroelectronics STM32MP135F-DK Discovery Board";
19 compatible = "st,stm32mp135f-dk", "st,stm32mp135";
[all …]

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