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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,kirkwood-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl",
10 "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl"
11 - reg: register specifier of MPP registers
14 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
24 mpp0 0 gpio, nand(io2), spi(cs)
28 mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
29 mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig)
[all …]
H A Dimg,pistachio-pinctrl.txt8 each. The GPIO banks are represented as sub-nodes of the pad controller node.
10 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
11 ../interrupt-controller/interrupts.txt for generic information regarding
15 --------------------------------------------
16 - compatible: "img,pistachio-system-pinctrl".
17 - reg: Address range of the pinctrl registers.
19 Required properties for GPIO bank sub-nodes:
20 --------------------------------------------
21 - interrupts: Interrupt line for the GPIO bank.
22 - gpio-controller: Indicates the device is a GPIO controller.
[all …]
H A Dmarvell,armada-370-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6710-pinctrl"
8 - reg: register specifier of MPP registers
16 mpp0 0 gpio, uart0(rxd)
17 mpp1 1 gpo, uart0(txd)
18 mpp2 2 gpio, i2c0(sck), uart0(txd)
19 mpp3 3 gpio, i2c0(sda), uart0(rxd)
20 mpp4 4 gpio, vdd(cpu-pd)
24 mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
26 mpp10 10 gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi)
[all …]
H A Dnxp,lpc1850-scu.txt2 --------------------------------------------------------
5 - compatible : Should be "nxp,lpc1850-scu"
6 - reg : Address and length of the register set for the device
7 - clocks : Clock specifier (see clock bindings for details)
9 The lpc1850-scu driver uses the generic pin multiplexing and generic pin
10 configuration documented in pinctrl-bindings.txt.
13 - function
14 - pins
15 - bias-disable
16 - bias-pull-up
[all …]
H A Daxis,artpec6-pinctrl.txt1 Axis ARTPEC-6 Pin Controller
4 - compatible: "axis,artpec6-pinctrl".
5 - reg: Should contain the register physical address and length for the pin
15 Required subnode-properties:
16 - function: Function to mux.
17 - groups: Name of the pin group to use for the function above.
37 uart0: uart0grp0, uart0grp1, uart0grp2
49 Optional subnode-properties (see pinctrl-bindings.txt):
50 - drive-strength: 4, 6, 8, 9 mA. For SD and NAND pins, this is for 3.3V VCCQ3.
51 - bias-pull-up
[all …]
H A Dberlin,pinctrl.txt1 * Pin-controller driver for the Marvell Berlin SoCs
4 controller register sets. Pin controller nodes should be a sub-node of
9 A pin-controller node should contain subnodes representing the pin group
14 is called a 'function' in the pin-controller subsystem.
17 - compatible: should be one of:
18 "marvell,berlin2-soc-pinctrl",
19 "marvell,berlin2-system-pinctrl",
20 "marvell,berlin2cd-soc-pinctrl",
21 "marvell,berlin2cd-system-pinctrl",
22 "marvell,berlin2q-soc-pinctrl",
[all …]
H A Dabilis,tb10x-iomux.txt5 -------------------
7 - compatible: should be "abilis,tb10x-iomux";
8 - reg: should contain the physical address and size of the pin controller's
13 --------------------
15 Functions are defined (and referenced) by sub-nodes of the pin controller.
16 Every sub-node defines exactly one function (implying a set of pins).
19 controller sub-nodes.
22 - abilis,function: should be set to the name of the function's pin group.
25 - GPIO ports: gpioa, gpiob, gpioc, gpiod, gpioe, gpiof, gpiog,
27 - Serial TS input ports: mis0, mis1, mis2, mis3, mis4, mis5, mis6, mis7
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/marvell/
H A Dcp110-system-controller.txt6 giving access to numerous features: clocks, pin-muxing and many other
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the CP110 system controller
14 SYSTEM CONTROLLER 0
18 -------
20 The Device Tree node representing this System Controller 0 provides a
23 - a set of core clocks
24 - a set of gateable clocks
28 - The first cell must be 0 or 1. 0 for the core clocks and 1 for the
30 - The second cell identifies the particular core clock or gateable
[all …]
/openbmc/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-armada-370.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
18 #include "pinctrl-mvebu.h"
21 MPP_MODE(0,
22 MPP_FUNCTION(0x0, "gpio", NULL),
23 MPP_FUNCTION(0x1, "uart0", "rxd")),
25 MPP_FUNCTION(0x0, "gpo", NULL),
26 MPP_FUNCTION(0x1, "uart0", "txd")),
28 MPP_FUNCTION(0x0, "gpio", NULL),
29 MPP_FUNCTION(0x1, "i2c0", "sck"),
[all …]
H A Dpinctrl-armada-cp110.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include "pinctrl-mvebu.h"
24 * - In Armada7K (single CP) almost all the MPPs are available (except the
26 * - In Armada8K (dual CP) the MPPs are split into 2 parts, MPPs 0-31 from
27 * CPS, and MPPs 32-62 from CPM, the below flags (V_ARMADA_8K_CPM,
32 V_ARMADA_7K = BIT(0),
41 MPP_MODE(0,
42 MPP_FUNCTION(0, "gpio", NULL),
49 MPP_FUNCTION(8, "uart0", "rxd"),
53 MPP_FUNCTION(0, "gpio", NULL),
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dhi6220-hikey.dts8 /dts-v1/;
11 /memreserve/ 0x05e00000 0x00100000;
17 compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
20 serial0 = &uart0; /* On board UART0 */
22 serial2 = &uart2; /* LS Expansion UART0 */
27 stdout-path = "serial3:115200n8";
30 memory@0 {
32 reg = <0x0 0x0 0x0 0x40000000>;
37 compatible = "linaro,optee-tz";
45 non-removable;
[all …]
H A Dsama5d3_uart.dtsi2 * sama5d3_uart.dtsi - Device Tree Include file for SAMA5D3 SoC with
10 #include <dt-bindings/pinctrl/at91.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/clock/at91.h>
16 serial5 = &uart0;
23 uart0 {
24 pinctrl_uart0: uart0-0 {
32 pinctrl_uart1: uart1-0 {
43 #clock-cells = <0>;
45 atmel,clk-output-range = <0 66000000>;
[all …]
H A Dmt7629-rfb.dts5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
13 compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
20 stdout-path = &uart0;
21 tick-timer = &timer0;
27 mediatek,gmac-id = <1>;
28 phy-mode = "gmii";
29 phy-handle = <&phy0>;
31 phy0: ethernet-phy@0 {
32 reg = <0>;
[all …]
/openbmc/linux/arch/arm/
H A DKconfig.debug1 # SPDX-License-Identifier: GPL-2.0
44 once the kernel has booted up - it's a one time check.
107 1 - undefined instruction events
108 2 - system calls
109 4 - invalid data aborts
110 8 - SIGSEGV faults
111 16 - SIGBUS faults
115 bool "Kernel low-level debugging functions (read help!)"
128 prompt "Kernel low-level debugging port"
132 bool "Kernel low-level debugging messages via Alpine UART0"
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dsama5d3_uart.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * sama5d3_uart.dtsi - Device Tree Include file for SAMA5D3 SoC with
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/at91.h>
12 #include <dt-bindings/mfd/at91-usart.h>
16 serial5 = &uart0;
23 uart0 {
24 pinctrl_uart0: uart0-0 {
32 pinctrl_uart1: uart1-0 {
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sifive/
H A Dsifive-blocks-ip-versioning.txt1 DT compatible string versioning for SiFive open-source IP blocks
4 strings for open-source SiFive IP blocks. HDL for these IP blocks
7 https://github.com/sifive/sifive-blocks
9 IP block-specific DT compatible strings are contained within the HDL,
10 in the form "sifive,<ip-block-name><integer version number>".
12 An example is "sifive,uart0" from:
14 https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43
17 auto-discovery, the maintainers of these IP blocks intend to increment
23 "sifive,uart0" to indicate that their driver is compatible with the
25 upstream sifive-blocks commits. It is expected that most drivers will
[all …]
/openbmc/linux/arch/powerpc/boot/
H A D4xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright 2002-2005 MontaVista Software Inc.
30 switch (pvr & 0xf0000ff0) { in chip_11_errata()
31 case 0x40000850: in chip_11_errata()
32 case 0x400008d0: in chip_11_errata()
33 case 0x200008d0: in chip_11_errata()
34 memsize -= 4096; in chip_11_errata()
49 memsize = 0; in ibm4xx_sdram_fixup_memsize()
50 for (i = 0; i < ARRAY_SIZE(sdram_bxcr); i++) { in ibm4xx_sdram_fixup_memsize()
57 dt_fixup_memory(0, memsize); in ibm4xx_sdram_fixup_memsize()
[all …]
/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-r16-nintendo-nes-classic.dts1 // SPDX-License-Identifier: GPL-2.0 OR X11
4 /dts-v1/;
5 #include "sun8i-a33.dtsi"
6 #include "sunxi-common-regulators.dtsi"
10 compatible = "nintendo,nes-classic", "allwinner,sun8i-r16",
11 "allwinner,sun8i-a33";
14 serial0 = &uart0;
18 stdout-path = "serial0:115200n8";
22 &uart0 {
24 * UART0 is available on two ports: PB and PF, both are accessible.
[all …]
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm283x.dtsi1 #include <dt-bindings/pinctrl/bcm2835.h>
2 #include <dt-bindings/clock/bcm2835.h>
3 #include <dt-bindings/clock/bcm2835-aux.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include <dt-bindings/soc/bcm2835-pm.h>
8 /* firmware-provided startup stubs live here, where the secondary CPUs are
11 /memreserve/ 0x00000000 0x00001000;
21 #address-cells = <1>;
22 #size-cells = <1>;
[all …]
/openbmc/linux/arch/arm/boot/dts/hisilicon/
H A Dsd5203.dts1 // SPDX-License-Identifier: GPL-2.0-only
8 /dts-v1/;
13 interrupt-parent = <&vic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 bootargs = "console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000";
22 serial0 = &uart0;
26 #address-cells = <1>;
27 #size-cells = <0>;
31 compatible = "arm,arm926ej-s";
[all …]
/openbmc/linux/arch/mips/boot/dts/brcm/
H A Dbcm3384_viper.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
5 compatible = "brcm,bcm3384-viper", "brcm,bcm33843-viper";
7 memory@0 {
11 reg = <0x06000000 0x02000000>,
12 <0x0e000000 0x02000000>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 mips-hpt-frequency = <300000000>;
[all …]
/openbmc/u-boot/arch/mips/dts/
H A Dgardena-smart-gateway-mt7688.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
12 compatible = "gardena,smart-gateway-mt7688", "ralink,mt7628a-soc";
13 model = "Gardena smart-Gateway-MT7688";
16 serial0 = &uart0;
20 memory@0 {
22 reg = <0x0 0x08000000>;
26 compatible = "gpio-leds";
31 default-state = "off";
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc4350-hitex-eval.dts9 * Released under the terms of 3-clause BSD License
13 /dts-v1/;
18 #include "dt-bindings/input/input.h"
19 #include "dt-bindings/gpio/gpio.h"
23 compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350";
26 serial0 = &uart0;
33 stdout-path = &uart0;
38 reg = <0x28000000 0x800000>; /* 8 MB */
42 compatible = "gpio-keys-polled";
43 poll-interval = <100>;
[all …]
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drv1126-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <arm64/rockchip/rockchip-pinconf.dtsi>
15 /omit-if-no-ref/
16 clk_out_ethernetm1_pins: clk-out-ethernetm1-pins {
23 /omit-if-no-ref/
24 emmc_rstnout: emmc-rstnout {
29 /omit-if-no-ref/
30 emmc_bus8: emmc-bus8 {
33 <0 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62p5-sk.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree file for the AM62P5-SK
4 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
9 /dts-v1/;
11 #include "k3-am62p5.dtsi"
14 compatible = "ti,am62p5-sk", "ti,am62p5";
24 stdout-path = &main_uart0;
29 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
30 <0x00000008 0x80000000 0x00000001 0x80000000>;
34 reserved-memory {
[all …]

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