Searched full:umctl2 (Results 1 – 7 of 7) sorted by relevance
4 $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#14 Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of19 For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a27 description: Synopsys DW uMCTL2 DDR controller v3.80a29 - description: Synopsys DW uMCTL2 DDR controller30 const: snps,dw-umctl2-ddrc36 DW uMCTL2 DDRC IP-core provides individual IRQ signal for each event":"107 compatible = "snps,dw-umctl2-ddrc";
411 /* Stop uMCTL2 before PHY is ready */ in stm32mp1_ddr_init()465 /* wait uMCTL2 ready */ in stm32mp1_ddr_init()492 /* enable uMCTL2 AXI port 0 and 1 */ in stm32mp1_ddr_init()
58 /* config the uMCTL2's registers */ in ddr_init()
65 /*step2 Configure uMCTL2's registers */ in ddr_init()
684 /* umctl2 config */
3009 F: Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
[all...]