| /openbmc/u-boot/doc/ |
| H A D | README.VSC3316-3308 | 2 Vitesse cross-point devices, VSC3316 and VSC3308 for board B4860QDS
8 VSC 3316/3308 is a low-power, low-cost asynchronous crosspoint switch capable of data rates upto 11…
10 …and 8 output ports. Programming of these devices are performed by two-wire or four-wire serial int…
14 On reset, VSC devices are in low-power state with all inputs, outputs and connections in an off sta…
15 First thing required is to program it to interface with either two-wire or four-wire interface.
16 …he interface is two-wire I2C serial interface. So the value in Interface mode register at address …
22 --------------------------
23 …two-wire or four-wire interface. In our case the interface is two-wire I2C serial interface. So th…
25 vsc_addr - Address of the VSC device on board.
29 ---------------------------------------------------------
[all …]
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| /openbmc/u-boot/drivers/w1/ |
| H A D | Kconfig | 5 menu "1-Wire support"
8 bool "Enable 1-wire controllers support"
12 Support for the Dallas 1-Wire bus.
17 bool "Enable 1-wire GPIO bitbanging"
21 Emulate a 1-wire bus using a GPIO.
24 bool "Enable 1-wire controller on i.MX processors"
28 Support the one wire controller found in some members of the NXP
30 There are currently two silicon variants:
33 Newer i.MX SoCs such as the i.MX6 do not have one wire controllers.
|
| /openbmc/linux/drivers/w1/slaves/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # 1-wire slaves configuration
6 menu "1-wire Slaves"
11 Say Y here if you want to connect 1-wire thermal sensors to your
12 wire.
17 Say Y here if you want to connect 1-wire
18 simple 64bit memory rom(ds2401/ds2411/ds1990*) to your wire.
23 Say Y or M here if you want to use a DS2405 1-wire
24 single-channel addressable switch.
25 This device can also work as a single-channel
[all …]
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| /openbmc/linux/Documentation/w1/ |
| H A D | w1-generic.rst | 2 Introduction to the 1-wire (w1) subsystem
5 The 1-wire bus is a simple master-slave bus that communicates via a single
6 signal wire (plus ground, so two wires).
18 - DS9490 usb device
19 - W1-over-GPIO
20 - DS2482 (i2c to w1 bridge)
21 - Emulated devices, such as a RS232 converter, parallel port adapter, etc
25 ------------------------------
29 - sysfs entries for that w1 master are created
30 - the w1 bus is periodically searched for new slave devices
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/sound/ |
| H A D | mt6359.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eason Yen <eason.yen@mediatek.com>
11 - Jiaxin Yu <jiaxin.yu@mediatek.com>
12 - Shane Chien <shane.chien@mediatek.com>
20 mediatek,dmic-mode:
23 Indicates how many data pins are used to transmit two channels of PDM
24 signal. 0 means two wires, 1 means one wire. Default value is 0.
26 - 0 # two wires
[all …]
|
| H A D | mt6358.txt | 10 - compatible - "string" - One of:
11 "mediatek,mt6358-sound"
12 "mediatek,mt6366-sound"
13 - Avdd-supply : power source of AVDD
16 - mediatek,dmic-mode : Indicates how many data pins are used to transmit two
17 channels of PDM signal. 0 means two wires, 1 means one wire. Default
23 compatible = "mediatek,mt6358-sound";
24 Avdd-supply = <&mt6358_vaud28_reg>;
25 mediatek,dmic-mode = <0>;
|
| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | intel,ce4100-lapic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rahul Tanwar <rtanwar@maxlinear.com>
28 [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf
32 const: intel,ce4100-lapic
37 interrupt-controller: true
39 '#interrupt-cells':
42 intel,virtual-wire-mode:
[all …]
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| /openbmc/linux/drivers/w1/masters/ |
| H A D | ds2482.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * ds2482.c - provides i2c to w1-master bridge(s)
7 * It is a I2C to 1-wire bridge.
8 * There are two variations: -100 and -800, which have 1 or 8 1-wire ports.
10 * http://www.maxim-ic.com/quick_view2.cfm/qv_pk/4382
25 * The APU bit controls whether an active pullup (controlled slew-rate
27 * a 1-Wire line from low to high. When APU = 0, active pullup is disabled
29 * only a single slave on the 1-Wire line.
34 "0-disable, 1-enable (default)");
36 /* extra configurations - e.g. 1WS */
[all …]
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| /openbmc/u-boot/arch/arm/mach-at91/include/mach/ |
| H A D | at91sam9x5.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Chip-specific header file for the AT91SAM9x5 family
5 * Copyright (C) 2012-2013 Atmel Corporation.
27 #define ATMEL_ID_TWI0 9 /* Two-Wire Interface 0 */
28 #define ATMEL_ID_TWI1 10 /* Two-Wire Interface 1 */
29 #define ATMEL_ID_TWI2 11 /* Two-Wire Interface 2 */
|
| H A D | sama5d4.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Chip-specific header file for the SAMA5D4 SoC
31 #define ATMEL_ID_MATRIX1 17 /* H32MX, 32-bit AHB Matrix */
32 #define ATMEL_ID_MATRIX0 18 /* H64MX, 64-bit AHB Matrix */
35 #define ATMEL_ID_SMC 22 /* Multi-bit ECC interrupt */
45 #define ATMEL_ID_TWI0 32 /* Two-Wire Interface 0 */
46 #define ATMEL_ID_TWI1 33 /* Two-Wire Interface 1 */
47 #define ATMEL_ID_TWI2 34 /* Two-Wire Interface 2 */
73 #define ATMEL_ID_TWI3 62 /* Two-Wire Interface 3 */
92 /* Reserved: 0xf0024000 - 0xf8000000 */
[all …]
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| H A D | sama5d3.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Chip-specific header file for the SAMA5D3 family
5 * (C) 2012 - 2013 Atmel Corporation.
23 #define ATMEL_ID_SMC 5 /* Multi-bit ECC Interrupt */
36 #define ATMEL_ID_TWI0 18 /* Two-Wire Interface 0 */
37 #define ATMEL_ID_TWI1 19 /* Two-Wire Interface 1 */
38 #define ATMEL_ID_TWI2 20 /* Two-Wire Interface 2 */
106 /* Reserved: 0xf003c000 - 0xf8000000 */
124 /* Reserved: 0xf804400 - 0xffffc00 */
153 /* Reserved: 0xfffffee0 - 0xffffffff */
|
| H A D | at91sam9g45.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Chip-specific header file for the AT91SAM9M1x family
29 #define ATMEL_ID_TWI0 12 /* Two-Wire Interface 0 */
30 #define ATMEL_ID_TWI1 13 /* Two-Wire Interface 1 */
45 #define ATMEL_ID_AESTDESSHA 28 /* AES + T-DES + SHA */
81 /* Reserved: 0xfffd8000 - 0xffffe1ff */
109 /* Reserved: 0xfffffdc0 - 0xffffffff */
|
| /openbmc/linux/Documentation/hwmon/ |
| H A D | lm85.rst | 79 - Philip Pokorny <ppokorny@penguincomputing.com>,
80 - Frodo Looijaard <frodol@dds.nl>,
81 - Richard Barrington <rich_b_nz@clear.net.nz>,
82 - Margit Schubert-While <margitsw@t-online.de>,
83 - Justin Thiessen <jthiessen@penguincomputing.com>
86 -----------
92 The LM85 uses the 2-wire interface compatible with the SMBUS 2.0
94 temperatures and five (5) voltages. It has four (4) 16-bit counters for
104 The temperatures measured are one internal diode, and two remote diodes.
127 ----------------
[all …]
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| H A D | asc7621.rst | 20 Andigilog has both the PECI and pre-PECI versions of the Heceta-6, as
21 Intel calls them. Heceta-6e has high frequency PWM and Heceta-6p has
23 Heceta-6e part and aSC7621 is the Heceta-6p part. They are both in
28 have used registers below 20h for vendor-specific functions in addition
29 to those in the Intel-specified vendor range.
31 Our conversion process produces a result that is reported as two bytes.
32 The fan speed control uses this finer value to produce a "step-less" fan
33 PWM output. These two bytes are "read-locked" to guarantee that once a
34 high or low byte is read, the other byte is locked-in until after the
37 sheet says 10-bits of resolution, although you may find the lower bits
[all …]
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| H A D | lm95234.rst | 22 Author: Guenter Roeck <linux@roeck-us.net>
25 -----------
27 LM95233 and LM95234 are 11-bit digital temperature sensors with a 2-wire
29 that can very accurately monitor the temperature of two (LM95233)
32 graphics processors or diode-connected 2N3904s. The chip's TruTherm
37 is provided within a range of -127 to +255 degrees (+127.875 degrees for
42 affects the hysteresis on all channels. The first two external sensors also
|
| /openbmc/linux/Documentation/i2c/ |
| H A D | summary.rst | 6 a protocol developed by Philips. It is a slow two-wire protocol (variable
12 e.g. TWI (Two Wire Interface), IIC.
14 The latest official I2C specification is the `"I2C-bus specification and user
16 published by NXP Semiconductors. However, you need to log-in to the site to
18 `here <https://web.archive.org/web/20210813122132/https://www.nxp.com/docs/en/user-guide/UM10204.pd…
39 .. kernel-figure:: i2c_bus.svg
57 video-related chips.
|
| /openbmc/bmcweb/redfish-core/schema/dmtf/installed/ |
| H A D | Sensor_v1.xml | 1 <?xml version="1.0" encoding="UTF-8"?>
2 <!---->
3 <!--################################################################################ -->
4 <!--# Redfish Schema: Sensor v1.10.1 -->
5 <!--# -->
6 <!--# For a detailed change log, see the README file contained in the DSP8010 bundle, -->
7 <!--# available at http://www.dmtf.org/standards/redfish -->
8 <!--# Copyright 2014-2024 DMTF. -->
9 <!--# For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright -->
10 <!--################################################################################ -->
[all …]
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| /openbmc/bmcweb/redfish-core/schema/dmtf/csdl/ |
| H A D | Sensor_v1.xml | 1 <?xml version="1.0" encoding="UTF-8"?>
2 <!---->
3 <!--################################################################################ -->
4 <!--# Redfish Schema: Sensor v1.10.1 -->
5 <!--# -->
6 <!--# For a detailed change log, see the README file contained in the DSP8010 bundle, -->
7 <!--# available at http://www.dmtf.org/standards/redfish -->
8 <!--# Copyright 2014-2024 DMTF. -->
9 <!--# For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright -->
10 <!--################################################################################ -->
[all …]
|
| /openbmc/qemu/qapi/ |
| H A D | introspect.json | 1 # -*- Mode: Python -*-
10 # See the COPYING file in the top-level directory.
17 # @query-qmp-schema:
19 # Command query-qmp-schema exposes the QMP wire ABI as an array of
28 # Furthermore, while we strive to keep the QMP wire format
29 # backwards-compatible across qemu versions, the introspection output
32 # non-variant, while another lists the same member only through the
42 # with different meta-types).
46 # QMP wire ABI, and therefore not returned by this command.
50 { 'command': 'query-qmp-schema',
[all …]
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| /openbmc/linux/drivers/block/drbd/ |
| H A D | drbd_protocol.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
33 P_SUPERSEDED = 0x18, /* Used in proto C, two-primaries conflict detection */
64 /* Only use these two if both support FF_THIN_RESYNC */
74 P_ZEROES = 0x36, /* data sock: zero-out, WRITE_ZEROES */
93 /* This is the layout for a packet on the wire.
154 u32 size; /* == bio->bi_size */
159 u32 size; /* == bio->bi_size */
166 * P_SUPERSEDED (proto C, two-primaries conflict detection)
193 /* supports TRIM/DISCARD on the "wire" protocol */
196 /* Detect all-zeros during resync, and rather TRIM/UNMAP/DISCARD those blocks
[all …]
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| /openbmc/linux/Documentation/driver-api/gpio/ |
| H A D | intro.rst | 13 Due to the history of GPIO interfaces in the kernel, there are two different
16 - The descriptor-based interface is the preferred way to manipulate GPIOs,
18 - The legacy integer-based interface which is considered deprecated (but still
21 The remainder of this document applies to the new descriptor-based interface.
23 integer-based interface.
29 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
37 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
38 non-dedicated pin can be configured as a GPIO; and most chips have at least
43 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
48 - Output values are writable (high=1, low=0). Some chips also have
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_eeprom.c | 27 /* AT24CM02 and M24M02-R have a 256-byte write page size.
31 #define EEPROM_PAGE_MASK (EEPROM_PAGE_SIZE - 1)
35 /* EEPROM memory addresses are 19-bits long, which can
37 * The upper 3 bits are sent as part of the 7-bit
38 * "Device Type Identifier"--an I2C concept, which for EEPROM devices
39 * is hard-coded as 1010b, indicating that it is an EEPROM
40 * device--this is the wire format, followed by the upper
41 * 3 bits of the 19-bit address, followed by the direction,
42 * followed by two bytes holding the rest of the 16-bits of
43 * the EEPROM memory address. The format on the wire for EEPROM
[all …]
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| /openbmc/linux/Documentation/driver-api/ |
| H A D | i2c.rst | 5 the "Inter-IC" bus, a simple bus protocol which is widely used where low
7 some vendors use another name (such as "Two-Wire Interface", TWI) for
8 the same bus. I2C only needs two signals (SCL for clock, SDA for data),
12 I2C is a multi-master bus; open drain signaling is used to arbitrate
18 structured around two kinds of driver, and two kinds of device. An I2C
38 .. kernel-doc:: include/linux/i2c.h
41 .. kernel-doc:: drivers/i2c/i2c-boardinfo.c
44 .. kernel-doc:: drivers/i2c/i2c-core-base.c
47 .. kernel-doc:: drivers/i2c/i2c-core-smbus.c
|
| /openbmc/linux/include/linux/ |
| H A D | w1.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * struct w1_reg_num - broken out slave device id
49 * struct w1_slave - holds a single slave device on the bus
51 * @owner: Points to the one wire "wire" kernel module.
84 * struct w1_bus_master - operations available on a bus master
92 * @touch_bit: the lowest-level function for devices that really support the
93 * 1-wire protocol.
94 * touch_bit(0) = write-0 cycle
95 * touch_bit(1) = write-1 / read cycle
108 * @triplet: Combines two reads and a smart write for ROM searches
[all …]
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| /openbmc/qemu/include/hw/i2c/ |
| H A D | arm_sbcon_i2c.h | 2 * ARM SBCon two-wire serial bus interface (I2C bitbang)
6 * Copyright (c) 2006-2007 CodeSourcery.
8 * Copyright (C) 2020 Philippe Mathieu-Daudé <f4bug@amsat.org>
10 * SPDX-License-Identifier: GPL-2.0-or-later
|